Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 47
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When one of their inputs changes, then the new output is determined from the table and is propagated on the output. The input values in a row ofthe table must correspond exactly to the values of the input ports for the row’s outputvalue to be selected. If a set of inputs appears on the ports for which there is no exactmatch, then the output will default to x. Any time delay to be associated with theprimitive is specified when instances of the primitive are defined. Because primitivescannot generate the value z, only two delays (rising and falling) can be specified perinstance.User-Defined Primitives241As can be seen, the definition of a user-defined primitive follows closely the definition of a module.
However, the keyword primitive introduces the definition and thekeyword endprimitive closes it. Declarations within a primitive can only be inputs,outputs, and registers (i.e. no inouts).udp_declarationprimitive udp_identifier ( udp_port_list);udp_port_declaration { udp_port_declaration }udp_bodyendprimitiveprimitive udp_identifier (udp_declaration_port_list);udp_bodyendprimitiveudp_port_listoutput_port_identifier, input_port_identifier {, input_port_identifier }udp_port_declarationudp_output_declarationudp_input_declarationudp_reg_declarationBeyond this point, the primitive definition departs greatly from that of a moduledefinition.
The primitive has no internal instantiations, assign statements, or alwaysstatements. (However, sequential primitives may have initial statements.) Rather, theprimitive requires a table definition whose syntax is partially detailed below.udp_bodycombinational_bodysequential_bodycombinational_bodytablecombinational_entry { combinational_entry }endtablecombinational_entrylevel_input_list: output_symbol;sequential_body[udp_initial_statement]table_sequential_entry {sequential_entry }endtableudp_initial_statementinitial output_port_identifier = init_val;242The Verilog Hardware Description LanguageReferences: sequential primitives 9.29.1.2 Describing Combinational Logic CircuitsThe usefulness of Example 9.1 might be rather low as nothing is stated about whathappens when there is an unknown (x) input on any of the inputs. Since the tablemade no mention of what happens when there is an x input, the output of the primitive will be x.
This is rather pessimistic in that if the other two inputs were both 1,then the output should be 1 regardless of the third input.The table enumeration allows for thespecification of 1,0, and x values in its inputand output sections. Further, it allows forthe specification of a don’t care in the tablemeaning that any of the three logic valuesare to be substituted for it when evaluatingthe inputs. Consider the expanded definition of the carry primitive shown inExample 9.2.
Here, the last six lines of thetable specify the output in the presence ofunknown inputs. For instance (third linefrom bottom of table), if carryIn and aInwere 1, and bIn was x, then carryOut willbe 1 regardless of the value of bIn. Ofcourse, if there were two unknowns on theinputs to this gate, then the output wouldbe unknown since there is no table entryspecifying what to do in that case.primitive carryX(output carryOut,input carryIn, aIn, bIn);table00000110011010010111011100xx00x0011xx11x 11endtableendprimitive0;0;0;1;0;1;1;1;0;0;0;1;1;1;The table may be abbreviated using the ?symbol to indicate iterative substitution of0,1, and x.
Essentially, the ? allows for us tostate that we don’t care what a certain value Example 9.2 A Carry Primitiveis, the other inputs will specify the output.The carry primitive example can be rewritten more compactly as shown inExample 9.3.User-Defined Primitives243We can read any line of the table in twoways. Taking the first line of the table as anexample, we can state that if the first twoinputs are both zero, then the third input canbe considered a don’t care and the output willbe zero. Second, we can mentally triplicatethe line substituting in values of 0, 1, and xfor the ?.
The shorthand provided by thedon’t care symbol improves the readability ofthe specification remarkably.primitive carryAbbrev(output carryOut,input carryIn, aIn, bIn);table00?0?0?0011?1?111?endtableendprimitive0;0;0;1;1;1;Example 9.3 A Carry Primitive WithShorthand Notation9.2 Sequential PrimitivesIn addition to describing combinational devices, user-defined primitives may be usedto describe sequential devices which exhibit level- and edge-sensitive properties.Since they are sequential devices, they have internal state that must be modeled with aregister variable and a state column must be added to the table specifying the behaviorof the primitive.
The output of the device is driven directly by the register. The outputfield in the table in the primitive definition specifies the next state.The level- and edge-sensitive primitives are harder to describe correctly becausethey tend to have far more combinations than normal combinational logic. Thisshould be evident from the number of edge combinations that must be defined.Should any of the edges go unspecified, the output will become unknown (x).
Thus,care should be taken to describe all combinations of levels and edges, reducing thepessimism.244The Verilog Hardware Description Language9.2.1 Level-Sensitive PrimitivesThe level-sensitive behavior of a latchis shown in Example 9.4. The latchoutput holds its value when the clockis one, and tracks the input when theclock is zero. Notable differencesbetween combinational and sequential device specification are the statespecification (surrounded by colons),and a register specification for theoutput.primitive latch(output reg q,inputclock, data);table//clock data state output01 :?:1;00 :?:0;1? :?:-;endtableendprimitiveTo understand the behavior specification, consider the first row.
When Example 9.4 A User-Defined Sequentialthe clock is zero and the data is a one,Primitivethen when the state is zero, one or x(as indicated by the ?), the output isone. Thus, no matter what the state is, the output (next state) depends only on theinput.
Line two makes a similar statement for having zero on the data input.If the clock input is one, then no matter what the data input is (zero, one, or x)there will be no change in the output (next state). This “no change” is signified by theminus sign in the output column.9.2.2 Edge-Sensitive PrimitivesThe table entries for modeling edgesensitive behavior are similar to thosefor level-sensitive behavior exceptthat a rising or falling edge must bespecified on one of the inputs. It isillegal to specify more than one edgeper line of the table. Example 9.5illustrates the basic notation with thedescription of an edge-triggered Dtype flip flop.primitive dEdgeFF(output reg q,inputclock, data);tableclock(01)(01)(0x)(0x)(?0)?endtableendprimitive//data0110?(??)state:? ::?::1::0::?::?:output0;1;1;0;-;-;The terms in parentheses representthe edge transitions of the clock variable. The first line indicates that onthe rising edge of the clock (01) whenthe data input is zero, the next state Example 9.5 Edge-Sensitive Behavior(as indicated in the output column)will be a zero.
This will occur regardless of the value of the current state. Line two ofUser-Defined Primitives245the table specifies the results of having a one at the data input when a rising edgeoccurs; the output will become one.If the clock input goes from zero to don’t care (zero, one, or x) and the data inputand state are one, then the output will become one. Any unspecified combinations oftransitions and inputs will cause the output to become x.The second to the last line specifies that on the falling edge of the clock, there is nochange to the output.
The last line indicates that if the clock line is steady at eitherzero, one, or x, and the data changes, then there is no output change.Similar to the combinational user-defined primitive, the primitive definition is verysimilar to that of a module. Following is the formal syntax for the sequential entries ina table within the primitive.udp_body|combinational_bodysequential_bodycombinational_bodytablecombinational_entry { combinational_entry}endtablecombinational_entrylevel_input_list: output_symbol;// see section 9.1sequential_body[udp_initial_statement]table_sequential_entry (sequential_entry }endtableudp_initial_statementinitial output_port_identifier = init_val;init_val1'b0 | 1'b1 | 1'bx | 1'bX | 1'B0 | 1'B1 | 1'Bx | 1'BX | 1 | 0sequential_entryseq_input_list: current_state : next_state ;seq_input_listlevel_input_list|edge_input_listlevel_input_listlevel_symbol {level_symbol}The Verilog Hardware Description Language246edge_input_list{level_symbol} edge_indicator {level_symbol}edge_indicator(level_symbol level_symbol)|edge_symbol//see section 9.3current_statelevel_symbolnext_state|output_symbol-// a literal hyphen, see textReferences: combinational primitives 9.1; edge symbols 9.39.3 Shorthand NotationExample 9.6 is another description of theedge-triggered flip flop in Example 9.5except that this one is written using someof Verilog’s shorthand notation for edgeconditions.primitive dEdgeFFShort(output reg q,inputclock, data);tableclockrr(0x)(0x)(?0)?endtableendprimitive//The symbol “r” in the table stands forrising edge or (zero to one), and “*” indicates any change, effectively substitutingfor “(??)”.
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