Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 50
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Table 10.6 shows the strengths printed out whenusing this statement. (Note that the simulation trace has been edited for display purposes.)The strength outputs in Table 10.6 have one of two formats. If a strength is listedwith a value, then the net is being driven by that value with the specified strength.The printing abbreviations for the strengths are listed in Table 10.4. Thus St1 indicates a strong 1, StH indicates a strong 1 or z, Pu0 indicates a pull 0, and PuX indicates a driver of strength pull driving an x. If two numbers are given with the value,then the net is being driven by multiple sources and the numbers indicate the minimum and maximum strength levels (see level numbers in Table 10.4) driving the net.For instance, at time 1100, net w1 is being driven by a strong (6) and pull (5) valueone.At time 100, all of the nets have unknown values on them, but notice that there is astrength associated with each of them corresponding to their driver’s declaration.Thus, address, dataIn, write, w1, and dataOut are all strong-strength signals,whereas w3 is a pull strength.
w4 is connected to g4 which is a pull-strength gate andto the tranif1 gate. Since it is connected to more than one gate output, we would haveexpected to see a range of strengths driven on it. Indeed this could be the case. However, it is not the tranif1 gate driving w4. Rather it is the bufif1 gate driving w4through the tranif1.The MOS gates do not have their own drive strength. They merely262The Verilog Hardware Description Languagepropagate the values and strengths at their input (with a possible reduction in strengthdepending on gate type and strength input).At time 500, we see net w1 listed as 56X, indicating that it is being driven by botha pull x and strong 1 driver.
This indication arises because the bufif1 gate (strong) isdriving an H (its control line is x) and the tranif1 gate is passing a pull-strength xfrom gate g4. The two combine to drive an x on w1. Since w1 and w4 are connectedtogether through the tranif1 gate, they both have the same indication.Following the operation of the sram at time 700, we see again that the strongstrength of the bufif1 gate transmitted through the tranif1 gate overrides the valuedriven by g4 onto w4, thus allowing for a new value to be saved. At 1300, we see thateven when address and write become unknown, the sram still holds its value.10.2.4 Resistive MOS GatesThe MOS gates can be modeled as either resistive or nonresistive devices. Nonresistivegates (nmos, pmos, cmos, tran, tranif0, and tranif1) do not effect the signal strengthfrom input to output (i.e.
between bidirectional terminals) except that a supplystrength will be reduced to a strong strength. In addition, pullup and pulldown gatesdrive their output with a pull strength. However, when the resistive model is used(rnmos, rpmos, rcmos, rtran, rtranif0, rtranif1), then a value passing through the gateundergoes a reduction in drive strength as enumerated in Table 10.7Consider another change in the sram specification where the tranif1 gate isdeclared to be a resistive transfer gate, rtranif1, with the following statement:Switch Level Modeling263rtranif1g2(w4, w1, address);Then with the detailed display statement shown in Example 10.3, we obtain the simulation results shown in Table 10.8.
(Note that the simulation trace has been editedfor display purposes.)Considering the values and strengths at time 500, we now see that w1 and w4 aredifferent because they are separated by a resistive device. On w1 there is a 36x, the 6arises from the bulif1 output driving a strong logic one and the 3 arises from g4 driving a logic zero as reduced from a pull drive (5) to a weak drive (3) by the rtranif1gate.It is important to note that this version of the sram does not work! The previousversions of the sram changed the stored value because the strong output of the bufif1gate overpowered the pull output of g4. But in this case, the rtranif1 gate reduces thestrong output to a pull output which does not overpower the output of g4.
Thus, g3does not change its output and the latching mechanism comprised of g3 and g4 doesnot capture the new value.10.3 Ambiguous StrengthsA possible way of representing a scalar net value is with two bytes of information; thefirst byte indicates the strength of the 0 portion of the net value, and the second byteindicates the strength of the 1 portion. The bit positions within each byte are numbered from most significant down to least significant. The bit position corresponds tothe strength level values as given in Table 10.4. The higher place value positions correspond to higher strengths. These are illustrated in Figure 10.3When a logicThe Verilog Hardware Description Language264gate is simulated, the value on its input in terms of zero, one, x, and z is determinedfrom the strength bytes. If thebit in either of the bytes is set when the rest ofthe bits are zero, or both bytes are zero, then the input is z. If thebits of bothbytes are zero, then for known values only one of these bytes will be non-zero.
Forunknown (x) values, both bytes will be non-zero.Ambiguous situations arise when multiple gates drive a common net, and in situations where there is an unknown value driving a tristate control input. These situations are modeled by the net taking on a range of values, i.e. contiguous bits in thetwo strength bytes are set.10.3.1 Illustrations of Ambiguous StrengthsWe will list a few examples to illustrate the reasoning process. Imagine the two bytesjoined together as shown in Figure 10.4Consider the following examples where two outputs drive the same net.
The representation used for the 0-strength and 1-strength bytes in the examples is that shownin Figure 10.4.<0-strength:1-strength>=logic value.Both the 0- and 1-strength bytes are given in binary notation. The logic value corresponding to each of the two strength bytes is given as one of 0, l, x, or z.Switch Level Modeling0100_0000:0000_0000 =00000_0000:0010_0000 =10100_0000:0000_0000 =0265output 1output2result on netIn the above case, output 1 is a strong zero and output 2 is a pull 1.
The result onthe net is a zero due to the strong driver.0000_0000:0110_0000 =10110_0000:0000_0000 =00111_1111:0111_1111 =xoutput 1output 2result on netIn this case, each output has an ambiguous strength, listed here as being bothstrong and pull. When these two outputs, one driving a one and the other driving azero, are combined on the net, the result is an x. All the bits between the values are setas shown in the result.0000_0000:0010_0000 =1 output 10000_0111:0111_1111 =x output 20000_0000:0110_0000 =1 result on netIn the above case, a pull 1 and an unknown with ambiguous strengths both drivethe net.
The drives range from a zero of medium capacitor (2) strength through astrong one. The result is a one with ambiguous strengths ranging between strong andpull.10.3.2 The Underlying CalculationsThe above illustrations were meant to give an intuitive feel for the operation of thesimulator in the presence of ambiguous strengths. In this section we present portionsof the miniSim example shown in full detail in Section 10.4.
The miniSim is a Verilog description of a very simple simulator that handles strengths. We will presentonly the portions of the Verilog description that do the strength calculations.Example 10.4 illustrates the log3 function which is called when a gate input is evaluated. The function converts the value inVal specified with two strength bytes into athree-valued logic.
In the description, the first strength byte is the zero byte and thesecond is the one byte. The first casez expression says that if none of the strength bitsare set, then the value is a x. The second expression states that if only some of the zerostrength bits are one, the value is a zero. Next, if only some of the one strength bits areone, the value is a one. If none of the above conditions hold, the value is unknown.The above function would be used when gates are evaluated.
Example 10.5 illustrates a task used to simulate a NAND gate.Although we will not describe all of the details of the task, we will describe enoughto give the basic understanding of the simulation. First we call the storeInVal task to266The Verilog Hardware Description Language` define Va10 3'd0`define Val1 3'd1`define ValX 3'd2// Convert a full strength value to a three-valued logic (0, 1 or X)function [1:0] log3(input[15:0] in Val);begincasez (in Val)16'b00000000_00000000: log3 = `ValX ;16'b???????0_00000000: log3 = `Val0;16'b00000000_???????0: log3 = `Val1;default: log3 = `ValX;endcaseendendfunctionExample 10.4 The log3 Function// Evaluate a 'Nand' gate primitive.task evalNand(input fanout); //first or second fanout indicatorbeginstoreInVal(fanout);// calculate new output valuein0 = log3(in0Val[evalElement]);in1 = log3(in1Val[evalElement]);out = ((in0 == `Va10) || (in1 == `Val0)) ?strengthVal(`Val1):((in0 == `ValX) || (in1 == `ValX)) ?strengthVal(`ValX):strength Val(`Val0);// schedule if output value is differentif (out != outVal[evalElement])schedule(out);endendtaskstore the input values to this element in the global memories in0Val and in1Val.
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