Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 54
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The box labeled ‘CRC’ should be implemented at the gate level,but all other boxes can be implemented at the behavioral level. The next sectiondescribes the format of the disk media, which will be followed by a description of thefunction of each of the boxes.Projects28711.2.2 Disk FormatThe format of the disk is shown in Figure 11.2. Figure 11.2a depicts the relationshipbetween the sectors and index holes used to generate the IDX signal, whileFigure 11.2b shows the format of each sector.
IDX is used to find the proper sector fora transfer. IDX pulses high at the beginning of every sector. You may assume for thisproject that when the simulation starts that the disk is just before the beginning ofsector 0. So the first IDX pulse signals the beginning of sector 0, the second the beginning of sector 1, etc. There are only 10 sectors on our disk.The other output from the disk media is RDDATA. RDDATA is the stream of data bitsmingled with the clock signal.
Module DECODE extracts the data from the clock signaland presents both to module Series-to-parallel (SerPar). Module SerPar then collectsthe bits into bytes and interprets them as per the sector format.At the beginning of each sector is a preamble. The preamble consists of 16 bytes of0’s. Immediately following the preamble is the sync byte (10000001).
The sync bytesignals the end of the preamble and the beginning of the data to the controller. This isnecessary because the head of the disk may have landed in the middle of the preambleand you may not have seen all 16 bytes of 0’s. When the sync byte is seen, the controller can start counting the bits and bytes of the rest of the sector.After the sync byte comes the actual data stored in the sector. There are 477 bytesof data stored in each sector. The least significant bit (LSB) of the each byte of data iswritten to (and read from) the disk first. Using Figure 11.3 as an example, if the byte5B hex (01011011) were stored on the disk, the bits would be read from the disk11011010.288The Verilog Hardware Description LanguageAt the end of each sector is a postscript which, like the preamble, consists of 16bytes of 0’s.The 2 bytes immediately preceding the postscript contain the checksumfor the data in the sector (See section 11.2.5.).
In our disk format, each sector contains 512 bytes. So the amount of data in a sector is 512 - 16 - 1 - 16 - 2 = 477 bytes.11.2.3 Function DescriptionsDecode: Decode takes as its input RDDATA, which is a stream of data bits mingled witha clock signal, from the disk media. Decode separates the clock from the data, andoutputs each of them to SerPar. The RDDATA signal at the beginning of the sector (inthe preamble) only contains clock pulses as shown in Figure 11.3.
The data embeddedin RDDATA is placed between the clock pulses. (No pulse between the clocks means azero bit of data, a one pulse between the clocks means a one bit of data.) Since thereare 16 bytes of zeros at the beginning, the controller has a chance to lock on to theclock signal embedded in RDDATA. The sync byte is the first byte that has any 1 bits init.The rightmost end of the RDDATA signal of Figure 11.3 shows what RDDATA wouldlook like if the byte 01011011 were being read from the disk.
The nominal period ofthe RDDATA clock pulses iswith a duty cycle of 1/8. For the sake of readability,the duty cycle is not accurately represented in Figure 11.3.SerPar: SerPar takes as its input IDX, the sector index signal from the disk media;the clock and data signals from Decode; and the sector number and go signals fromthe simulation interface. On the positive edge of go, SerPar resets the CRC, and beginscounting IDX pulses until the proper sector is found. Once the proper sector is found,SerPar begins monitoring the data line from Decode for the sync byte. SerPar thentransfers the data a bit at a time to CRC, and a byte at a time to FIFO.
When it hasreceived all the data from the sector it compares the 16-bit checksum stored after thedata in the sector to the one that has just been computed by CRC for the data. If thetwo checksums are the same, then SerPar raises the done signal for the simulationinterface. If the two checksums are different, then SerPar raises the err signal for thesimulation interface.Projects289CRC: CRC takes the data one bit at a time from SerPar, and computes its checksumon the data bytes. The CRC should be reset by SerPar before the data from the sector isread in. You must implement CRC at the gate/flip-flop level.FIFO: FIFO is a 16-byte First In, First Out queue.
It serves as a buffer for the databetween SerPar, and DMA and memory. Once it receives a byte from SerPar, FIFOshould signal to DMA that a transaction is necessary. When DMA has gained access tomain memory, FIFO will transfer its contents to memory via DMA.DMA: DMA transfers bytes from FIFO to main memory. When FIFO signals that atransaction is necessary, DMA arbitrates with main memory for control of the memorybus. The DMA asserts hrq to request the bus.
The memory asserts hack (how appropriate are these names?) to tell the DMA it can use the bus. Once DMA has gained controlof the bus, it transfers the bytes of data from FIFO to main memory. The data is transferred by asserting the address and data lines and then memw. When FIFO has nomore data, DMA relinquishes control of the memory bus by deasserting hrq and waitsuntil FIFO again signals that a transaction is necessary.
Figure 11.4 shows the protocolfor gaining control of the bus, and then strobing the data into memory. Assume thatthe data will be placed in the first N bytes of memory, so you won’t have to worry290The Verilog Hardware Description Languageabout getting a starting address or block size. In the real world, controllers need toknow where to place data and how much data is going to be placed.Projects29111.2.4 Reality Sets In…We told you in the Disk Format section that the clock embedded in the RDDATA signal has a nominal period ofand that the data is put halfway between clockpulses. “No big deal,” you say, “when I get a clock pulse, I’ll waitand see ifRDDATA is high.
If it is, I have a 1. If not, I have a 0.” If you write a simulation wherethe clock comes along everyand the data is exactly between the clock pulses, thesimulation works, and you’re happy. But real disk drives depend on motors and magnetic media, so sometimes the clock comes along atand sometimes it comesalong atwith the data atDisk drive controllers use something called a phase-locked loop (PLL) to latch ontothe frequency of the clock and to adjust to its variations as the motor changes speedand the bits jitter around. You need to come up with a way to find the data in betweenthe clock pulses without depending on the clock pulses being exactlyapart.
TheRDDATA from our input modules is going to vary like RDDATA does in the real world.In order to make the problem a little easier though, we’ll guarantee that the clockperiod will be+/- 5%, and that the center of the data will be within +/- 5% of thecenter of the pulses. Make sure your Decode module can lock onto the embeddedclock during the preamble and hold onto it even as the frequency changes slightly. Inreal life, that’s why the preamble is there. A Verilog description that produces thesewaveforms is provided on the e-mail reflector.11.2.5 Everything You Always Wanted to Know about CRC’sThe disk will use a 16 bit cyclic redundancy check (CRC) word calculated from thedata bytes by the binary polynomial:The CRC computation uses a shift register and XOR gates.
Unlike a normal shift register, some of the stages shift in the previous bit XOR’d with the bit being shifted out ofthe shift register. The bits from the data stream are shifted in from the left. Numbering the bits from 1 on the left to 16 on the right, the input to the first, sixth, and thirteenth bits of the register are XOR’d with the output of the sixteenth bit.The shift register is initialized to zero.
After the entire data stream has been readin, the content of the shift register is the checksum for the sector. It is compared bitby-bit with the checksum stored with the sector on the disk. If the two checksumsmatch, then it is unlikely that a bit error has occurred, and the controller can transferthe data to memory. If the checksums do not match, then some bit(s) of data musthave been corrupted. The controller should then signal that an error has occurred.The CRC should be build out of XOR gates and flip-flop modules (the FF’s may bedescribed behaviorally).292The Verilog Hardware Description Language11.2.6 Supporting Verilog ModulesThere are several Verilog modules providing the stream of data and clock comingfrom the disk.
Some modules will have correct data and some erroneous data; the filenames are “correctx.v” and “errorx.v.” The memory and bus controller modules areprovided in “memory.v.” The module declarations for these files are shown inFigure 11.5. The Verilog descriptions mentioned here can be found on the e-mailreflector.ATutorial Questionsand DiscussionThis appendix contains questions, answers, and discussion to accompany Chapter 1,the tutorial introduction.
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