Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 57
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It is always one. The others are asserted low; a zeroturns on a display segment. The segment bits are shown in order (either segments a-for f-a). Figure out which is which from what you know about displays.A.4 Sequential CircuitsThese questions are to be used with Section 1.3. The first question includes a fairlylengthy discussion of writing a description of a sequential circuit. The others assumemore background.The Verilog Hardware Description Language306A.14Design a two-bit counter. The circuit will count either up or down through the2-bit binary number range. Your circuit has two external inputs:updetermines the count direction. It is asserted high.reset asynchronously sends the circuit to state 0. It is asserted low.The counter will sequence between the four states: 0, 1, 2, 3 as follows:if up =if up =Thus the circuit implements a counter that counts from 0 to 3, or 3 to 0, over andover.
It can be asynchronously reset to 0, by asserting reset.What states and state transitions exist? A state transition diagram is shown inFigure A.3.How to represent the states? Let’s use two bits to represent the states. An obviousstate assignment is to have 00 represent state 0, 01 represent 1,10 represent 2, and 11represent 3.Do this — Write the Verilog description for this counter. Here is the module header:module counter_2_bit(up, clk, rst, count);inputup, clk, rst;output [1:0] count;reg[1:0] count;An answer follows on the next page.Why is the default: needed in the answer to the counter description in the aboveproblem? Consider both simulation and synthesis when answering.A.16 Create a testbench module for Example 1.6. You will need to include a clock forthe circuit; use the one in Example 1.9.
Your testbench module should reset thecircuit and then provide the following inputs to the circuitA.15307module counter_2_bit//Answer to problem A. 14(inputup, clk, rst,// Declarationsoutput reg [1:0] count);reg[1:0]nextCount;always @(up, count)case (count)0: beginif (up) nextCount = 1;else nextCount = 3;end1: beginif (up) nextCount = 2;else nextCount = 0;end2: beginif (up) nextCount = 3;else nextCount = 1;end3: beginif (up) nextCount = 0;else nextCount = 2;enddefault:nextCount = 0;endcasealways @(posedge clk, negedge rst)if(~rst)count <= 0;elsecount <= nextCount;endmodule0, 0, 1, 0, 1, 1, 1, 1, 0, 0.Simulate the fsm to show that it correctly transits through its states.A.17 Ifyou changed the non-blocking assignments (<=) to blocking assignments (=)in Example 1.6, would there be any difference in the outcome of a simulation.Explain.The Verilog Hardware Description Language308A.18 Some simulators have a single step mode where individual events are simulated.figure out which of the two concurrent assignments is done first in the else inExample 1.7.
Why can’t we give you an answer as to which one is done first?A.19 Here’s one way to swap values in registers.reg[7:0] a, b, temp;always begintemp = a;a = b;b = temp;Rewrite this using only registers a and b (i.e., get rid of temp).A.5 Hierarchical DescriptionsThese questions are to be used with Section 1.4.A.20 What differences will be found when simulating Examples 1.13, 1.3, and 1.5?A.21 Write the whole board example (Examples 1.3, 1.8, 1.9, and 1.10) as onemodule.
Use behavioral models (always and initial) as much as possible. Explainthe order of execution at the start of a simulation.BLexical ConventionsVerilog source text files consist of a stream of lexical tokens separated by white space.The spacing of tokens is free format — the specific choice of tabs, spaces, or newlinesto separate lexical tokens is not important to the compiler. However, the choice isimportant for giving a readable structure to the description. It is important that youdevelop a consistent style of writing your Verilog descriptions. We offer the examplesin the book as a starting point to develop your own personal style.The types of lexical tokens in the language are: white space, comments, operators,numbers, strings, identifiers, and keywords.
This Appendix will discuss each of these.B.1 White Space and CommentsWhite space is defined as any of the following characters: blanks, tabs, newlines, andformfeeds. These are ignored except for when they are found in strings.There are two forms of comments. The single line comment begins with the twocharacters // and ends with a newline. A block comment begins with the two characters /* and ends with the two characters */.
Block comments may span several lines.However, they may not be nested.The Verilog Hardware Description Language310B.2 OperatorsOperators are single, double or triple character sequences that are used in expressions.Appendix C lists and defines all the operators.B.3 NumbersConstant numbers can be specified in decimal, hexadecimal, octal, or binary. Theymay optionally start with a + or -, and can be given in one of two forms.The first form is an unsized decimal number specified using the digits from thesequence 0 to 9.
Although the designer may not specify the size, Verilog calculates asize for use in an expression. In an expression, the size is typically equivalent to thesize of the operator’s other (sized) operand. The appropriate number of bits, startingfrom the least significant bit, are selected for use. Appendix C.4 lists a set of rules forcalculating the size.The second form specifies the size of the constant and takes the form:aa...a 'sf nn…nwhere:Unknown and high impedance values may be given in all but the decimal base.
Ineach case, the x or z character represents the given number of bits of x or z. i.e. inhexadecimal, an x would represent four unknown bits, in octal, three.311Normally, zeros are padded on the left if the number of bits specified in nn…n isless than specified by ss…s. However, if the first digit of nn…n is x or z, then x or z ispadded on the left.An underline character may be inserted into a number (of any base) to improvereadability. It must not be the first character of a number. For instance, the binarynumber:12 'b 0x0x_1101_0zx1is more readable than:12 'b 0x0x11010zx1.Examples of unsized constants are:7927d9'h 7d9'o 7746// a decimal number// illegal, hexadecimal must be specified with 'h// an unsized hexadecimal number// an unsized octal numberExamples of sized constants are:12 'h x // a 12-bit unknown number8 'h fz // equivalent to the binary: 8 'b 1111_zzzz10 'd 17 // a ten-bit constant with the value 17.Examples of signed and negative constants are:-6 'd 5 // a six-bit constant with the value of -5 (i.e., 111011)6 'd -5 // illegal3 'sd 7 //a three-bit signed constant with value -1.
i.e., deciml 7 represented inthree bits is 111. The s indicates that the number should be treated assigned, which makes it minus 1.4 'sh F // a four-bit signed constant with the value -1. i.e., hex F is representedin four bits as 1111. The s indicates that the number should be treatedas signed, which makes it minus 1.B.4 StringsA string is a sequence of characters enclosed by double quotes.
It must be containedon a single line. Special characters may be specified in a string using the “\” escapecharacter as follows:The Verilog Hardware Description Language312\n\t\\\"\dddnew line character. Typically the return key.tab character. Equivalent to typing the tab key.is the \ character.is the " characteris an ASCII character specified in one to three octal digits.B.5 Identifiers, System Names, and KeywordsIdentifiers are names that are given to elements such as modules, registers, ports,wires, instances, and begin-end blocks.
An identifier is any sequence of letters, digits,and the underscore (_) symbol except that:the first character must not be a digit, andthe identifier must be 1024 characters or less.Upper and lower case letters are considered to be different.System tasks and system functions are identifiers that always start with the dollarsymbol. A partial list of system tasks and functions is provided in Appendix F.Escaped identifiers allow for any printable ASCII character to be included in thename.
Escaped identifiers begin with white space. The backslash (“\”) character leadsoff the identifier, which is then terminated with white space. The leading backslashcharacter is not considered part of the identifier.Examples of escaped identifiers include:\bus-index\a+bEscaped identifiers are used for translators from other CAD systems.
These systems may allow special characters in identifiers. Escaped identifiers should not beused under normal circumstances313CVerilog OperatorsC.1Table of OperatorsTable 3.1 Verilog OperatorsOperatorSymbol{,}NameDefinitionCommentsConcatenationJoins together bitsfrom two or morecomma-separated expressionsConstants must be sized. Alternateform uses a repetition multiplier. {b, {3{a, b}}} is equivalent to {b, a, b, a, b, a,b}.+AdditionSums two operands.Register and net operands are treated asunsigned.
Real and integer operandsmay be signed. If any bit is unknown,the result will be unknown.-SubtractionFinds differencebetween twooperands.Register and net operands are treated asunsigned. Real and integer operandsmay be signed. If any bit is unknown,the result will be unknown.Unary minusChanges the signof its operandRegister and net operands are treated asunsigned. Real and integer operandsmay be signed. If any bit is unknown,the result will be unknown.The Verilog Hardware Description Language316Table 3.1 Verilog Operators*MultiplicationMultiply twooperands.Register and net operands are treated asunsigned. Real and integer operandsmay be signed. If any bit is unknown,the result will be unknown./DivisionDivide two operandsRegister and net operands are treated asunsigned. Real and integer operandsmay be signed.
If any bit is unknown,the result will be unknown. Divide byzero produces an x.%ModulusFind remainderRegister and net operands are treated asunsigned. Real and integer operandsmay be signed. If any bit is unknown,the result will be unknown.**PowerRaise to thepower ofResult = base ** exp. Result will beunsigned if the base and exp are also. Itwill be a real if either operand is a real,integer, or signed value.>Greater thanDetermines relative valueRegister and net operands are treated asunsigned.
Real and integer operandsmay be signed. If any bit is unknown,the relation is ambiguous and the resultwill be unknown.>=Greater than orequalDetermines relative valueRegister and net operands are treated asunsigned. Real and integer operandsmay be signed. If any bit is unknown,the relation is ambiguous and the resultwill be unknown.<Less thanDetermines relative valueRegister and net operands are treated asunsigned.
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