Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 56
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The delay we include in the description needs to be longerthan the longest delay through the gates. In this case, setting it to six would worksince the longest path from inputs to outputs is five. You could also set it to #3072with no change in the results.The following description is correct.299module top;wired, e, f;rega, b, c;notandor#1 gl(d,b);#2 g2(e, a, d);#2 g3(f,e, c);//initial begin"a=%b, b=%b, c=%b, d=%b, e=%b, f=%b\n",a, b, c, d, e, f);a = 1;b = 0;c = 0;#20 b = 1;#20 a = 0;#20 c = 1;// initialization// first change of input//second change of input// third change of input#20endendmoduleThe simulation results should look like this:1a=1, b=0, c=0, d=1, e=x, f=x3 a=1, b=0, c=0, d=1, e=1, f=x5 a=1,b=0,c=0,d=1,e=1,f=120 a=1,b=1,c=0,d=1,e=1,f=121 a=1,b=1,c=0,d=0,e=1,f=123 a=1,b=1,c=0,d=0,e=0,f=125 a=1, b=1, c=0, d=0, e=0, f=040 a=0,b=1,c=0,d=0,e=0,f=060 a=0, b=1, c=1, d=0, e=0, f=062 a=0,b=1,c=1,d=0,e=0,f=1A.2 Type in the folowing example andname the file adder.v.
It implements module halfadder(outputthe add function for two bits, producinputing a sum and a carry out. Create amodule to test this halfadder modulexor#1and instantiate them both in a testand#2bench module.endmodulecOut, sum;a, b);(sum, a, b);(cOut, a, b);The Verilog Hardware Description Language300The first line gives the name of the module, and lists the inputs and outputs. Thenext two lines define which are inputs and which are outputs.
Essentially it definestwo outputs and two inputs, each to be single bit quantities.Then we instantiate an XOR gate, with a and b as inputs, and sum as the output.The XOR gate is specified to have a delay of one time unit. That is, one time unit afteran input changes, the output might change. The and gate is similar, but with a delayof two time units.
Finally, we have the endmodule statement which indicates the endof the module description.Do This — Create the testadder module. The idea is that we’re going to connectthis module to the halfadder module and have this module test it. Both modules willbe instantiated within another module called system.Discussion: A testadder module is shown below. The initial statement introduces abehavioral block; these blocks can be read much like you would read C (yes, there aremany differences). The initial statement indicates that the block should only be executed once.When the initial statement starts, it executes thestatement (as describedin the previous question), and assigns x and y to be 0.
“#10” tells the simulator to waitfor 10 time units and then continue execution. In 10 more time units, x is set to 1.After another 10, y is set to 1. Finally, after another 10, x is set to 0. Essentially, overthe course of execution, x and y will have all four combinations of inputs for the halfadder, and there is enough time for these values to propagate through the gates in theadder module.causes the simulator to exit after another 10 time units.module testadder(output reg x,y,inputc, s);initial begin"x = %b, y = %b, Sum = %b, Carry = %b", x, y, s, c);x = 0;y = 0;#10x = l;#10y = l;#10x = 0;#10endendmodule301Finally, we need to connect the two modules together as shown in module system.The wire declaration defines four wires with the given names.module system;wireCarryOut, SumOut, in1, in2;halfaddertestadderendmoduleAddUnit (CarryOut, SumOut, in1, in2);TestUnit (in1, in2, CarryOut, SumOut);The module system is the top level of our design — it has no inputs or outputs andthe other modules are instantiated within it.
When the modules are instantiated,instance names are given to each: halfadder is named AddUnit, and testadder isnamed TestUnit. In effect, we have wired up a half adder module to a module thatcreates inputs for the half adder. Outputs from the half adder are monitored by thetest module.Consider the two statements from module system:halfaddertestadderAddUnit (CarryOut, SumOut, in1, in2);TestUnit (inl, in2, CarryOut, SumOut);Do not think of this as executing the halfadder, then executing the testadder — theseare not function calls.
Rather, these define that an instance of each of these modules isto be connected together using wires as shown. Reversing the order of the two statements has no effect.Do This — Run the simulator on this file. The simulator should display all theinputs and outputs, with the simulation time. Reason your way through the executionof these modules. Note that the testadder module will set x and y to certain values andthen wait 10 time units. During that time, the XOR and AND gates in the halfaddermodule will execute and change their outputs.
And then the testadder module willcontinue to execute.A. What effect do the time delays in module halfadder have? Play around withthem (they’re integers). Make them 1.B. Remove thecommand; what changes?C. Then also change the initial to always; what changes?A.3 Example 1.2 is duplicated here as Example A.1.
Expand the initial statement tocover all input patterns. Simulate the circuit, and create a truth table or K-mapfor this circuit. Draw out the seven-segment display patterns. Is the functioncorrect?The Verilog Hardware Description Language302Discussion: the example has four inputs and thusdistinct input patterns.Make sure all patterns are assigned to registers A, B, C, and D with enoughtime for the values to propagate to the output.A.4 In the same example, change the gate types to AND and OR.
Resimulate.Discussion: Use DeMorgan’s theorem to convert from NAND-NAND logic toAND-OR.In the same example, change the gate types to NOR-NOR.Discussion:Use DeMorgan’s theorem.A.6 Simulate Example A.1 using #6 instead of #1 for the gate delays. The resultswill not be the same. Explain.A.7 Design a circuit using only NAND gates implementing the driver for segment a.Test it using the simulator.A.5module binaryToESegSim;wireeSeg, p1, p2, p3, p4;regA, B, C, D;nand #1g1 (pl, C,~D),g2 (p2, A, B),g3 (p3, ~B, ~D),g4 (p4, A, C),g5 (eSeg, p1, p2, p3, p4);initialbegin// two slashes introduce a single line comment"A = %b B = %b C = %b D = %b, eSeg = %b",A, B, C, D, eSeg);//waveform for simulating the binaryToESeg driver#10 A = 0; B = 0; C = 0; D = 0;#10 D = 1;#10 C = 1; D = 0;#10endendmoduleExample A.1 A Copy of Example 1.2303A.2 Testbench ModulesThe questions in this section are to be used with Section 1.1.4.A.8 In problem A.4 you developed an AND-OR version of Example A.1.
Change it touse the testbench approach. Simulate using a complete set of test vectors.Inproblem A.5 you developed an NOR-NOR version of Example A.1. Change itA.9to use the testbench approach. Simulate using a complete set of test vectors.A. 3 Combinational Circuits Using alwaysThese problems are to be used with Section 1.2. Problem A.11 includes a detaileddiscussion of problems encountered when writing such descriptions.A.10 Substitute module binaryToESeg_Behavioral into the testBench module ofExample 1.4. Compare the simulation results with those of the original example.
What is different?A.11 At this point, we have only covered the basic issues in describing combinationalcircuits using the always block. For a more detailed discussion, refer back toChapter 2.Do this — write a module usingbehavioral modeling techniques todescribe the circuit in Figure A.2.Compile the module for simulationand synthesis. Is it functionally correct? If your circuit will not synthesize, read on to see if you hit upon any of thesecommon mistakes!Lack of Assignment — You might run intothis particular problem if you assume that registervalues start at or default to 0. This is how ourcode would look if this assumption of f=0 bydefault was made.module andOr(output reg f,inputa, b, c);always @(a, b, c)if (c + (a&~b))The simulator will initially assign f to have thef=l;value x. It will keep that value until it is assignedendmoduleto 1, and will never assign it to zero.
Obviously,we simply put in an else that will assign f to be 0. When describing modules for synthesis, it’s a good general rule that for every if there should be an else to tell the logicwhat to do should that statement not be TRUE. Like this:The Verilog Hardware Description Language304module andOr(output reg f,inputa, b, c);always @(a, b, c)if (c + (a&~b))f = l;else f = 0;endmoduleBut we can break that rule. Here is a correct always block for the above problemwith out an else. The trick is that the statement assigning f to zero creates a defaultvalue for f, the rest of the description can then concentrate on when to set it to 1.always @(a, b, c) beginf = 0;if (c + (a&~b))f = l;endMissing Input Sensitivity — This is generally a simple matter that something wasleft out.
A fundamental characteristic of combinational circuits is that they are alwayssensitive to all of their inputs. That is, a change on any input could cause a change onthe output. Thus, the event statement (“@”) in the always block has to include all ofthe combinational inputs. The expression in the parentheses of the event statement iscalled the sensitivity list. The following is how not to write the sensitivity list.module andOr(output reg f,inputa, b, c);always @(a,c)if (c)f = 1;elsef = a &~b;endmodule//OOPS! Forgot b! This should be (a, b, c)This will have the effect of not updating the output when b changes, leaving itwherever it was until either a or c change. The simulation will give bad results. A synthesis tool will not think of this as a combinational circuit.
It will think: anytime bchanges, the circuit has to remember the previous before b changed. This requiresmemory in the circuit. Combinational circuits do not have memory; their outputs area function only of the current inputs.305A.12 Rewrite Example 1.5 starting with “eSeg = 0”. Then specify the conditions whenit is to be set to one. The module should use only a single always block.
Theninsert into a testBench module and simulate to show correct function.A.13 A case statement is often used in synthesizable Verilog descriptions.Example A.2 is a Verilog description for a BCD to seven segment display module using a case statement. Read ahead in section 3.4.2 to see how the case statemodule BCDtoSevenSeg(output reg [7:0] led,input[3:0] bcd);always @(bcd)case (bcd)0 : led = 'h81;1 : led = 'hcf;2 : led = 'h92;3 : led = 'h86;4 : led = 'hcc;5 : led = 'ha4;6 : led = 'ha0;7 : led = 'h8f;8 : led = 'h80;9 : led = 'h8c;default:led = 'bxxxxxxxx;endcaseendmoduleExample A.2 Verilog Description of BCD to Seven Segment Displayment works.Do this — Since this module only decodes the digits 0 through 9, change it to alsodecode and display the digits A through F.Hints: Ignore the top-most bit.
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