Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 52
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Continue this loop// until no more events to execute.// For each event executed, evaluate the two fanout elements if present.task executeEvents;reg [15:0] newVal;beginsimTime = 0;while (currentList)begineventElement = currentList;currentList = schedList[eventElement];schedPresent[eventElement] = 0;newVal = outVal[eventElement];if (DebugFlags[3])display("At %0d,%0d Element %0d, type %0s, changes to %s(%b_%b)",pattern, simTime,eventElement, typeString(eleType[eventElement]),valString(newVal), newVal[15:8], newVal[7:0]);if (fo0Index[eventElement]) evalFo(0);if (fo1Index[eventElement]) evalFo(1);if (! currentList) // if empty move to next time unitbegincurrentList = nextList;nextList = 0;simTime = simTime + 1;endendendendtask// Evaluate a fanout element by testing its type and calling the// appropriate evaluation routine.task evalFo;input fanout; //first or second fanout indicatorbeginevalElement = fanout ? fo1Index[eventElement]:fo0Index[eventElement];if(DebugFlags[1])display("Evaluating Element %0d type is %0s",evalElement, typeString(eleType[evalElement]));case (eleType[evalElement])`Nand: evalNand(fanout);275276The Verilog Hardware Description Language`DEdgeFF: evalDEdgeFF(fanout);`Wire: evalWire(fanout);endcaseendendtask// Store output value of event element into// input value of evaluation element.task storeInVal;input fanout; //first or second fanout indicatorbegin// store new input valueif (fanout ? fo1TermNum[eventElement] : fo0TermNum[eventElement])in1Val[evalElement] = outVal[eventElement];elsein0Val[evalElement] = outVal[eventElement];endendtask// Convert a given full strength value to three-valued logic (0,1 or X)function [1:0] log3;input [15:0] in Val;casez (inVal)16'b00000000_00000000: log3 = `ValX;16'b???????0_00000000: log3 = `Val0;16'b00000000_???????0: log3 = `Val1;default:log3 = `ValX;endcaseendfunction// Convert a given full strength value to four-valued logic (0,1, X or Z),// returning a 1 character stringfunction [8:1] valString;input [15:0] in Val;case (log3(inVal))`Val0: valString = "0";`Val1: valString = "1";`ValX: valString = (inVal & 16'b11111110_11111110) ? "X": "Z";endcaseendfunction// Coerce a three-valued logic output value to a full output strength value// for the scheduling of the evaluation elementfunction [15:0] strengthVal;input [1:0] logVal;Switch Level Modeling277case (log Val)`Val0: strengthVal = eleStrength[evalElement] & 16'b11111111_00000000;`Val1: strengthVal = eleStrength[evalElement] & 16'b00000000_11111111;`ValX: strengthVal = fillBits(eleStrength[evalElement]);endcaseendfunction// Given an incomplete strength value, fill the missing strength bits.// The filling is only necessary when the value is unknown.function [15:0] fillBits;input [15:0] val;beginfillBits = val;if(log3(val) ==`ValX)begincasez (val)16'b1???????_????????: fillBits = fillBits | 16'b11111111_00000001;16'b01??????_????????: fillBits = fillBits | 16'b01111111_00000001;16'b001?????_????????: fillBits = fillBits | 16'b00111111_00000001;16'b0001????_????????: fillBits = fillBits | 16'b00011111_00000001;16'b00001???_????????: fillBits = fillBits | 16'b00001111_00000001;16'b000001??_????????: fillBits = fillBits | 16'b00000111_00000001;16'b0000001?_????????: fillBits = fillBits | 16'b00000011_00000001;endcasecasez (val)16'b????????_1???????: fillBits = fillBits | 16'b00000001_11111111;16'b????????_01??????: fillBits = fillBits | 16'b00000001_01111111;16'b????????_001?????: fillBits = fillBits | 16'b00000001_00111111;16'b????????_0001????: fillBits = fillBits | 16'b00000001_00011111;16'b????????_00001???: fillBits = fillBits | 16'b00000001_00001111;16'b????????_000001??: fillBits = fillBits | 16'b00000001_00000111;16'b????????_0000001?: fillBits = fillBits | 16'b00000001_00000011;endcaseendendendfunction// Evaluate a 'Nand' gate primitive,task evalNand;input fanout; //first or second fanout indicatorbeginstoreInVal(fanout);// calculate new output valuein = log3(in0Val[evalElement]);in1 = log3(in1Val[evalElement]);278The Verilog Hardware Description Languageout = ((in0 = = `Val0) || (in1 = = `Val0)) ?strengthVal(`Val1):((in0 = = `ValX) || (in1 = = `ValX)) ?strengthVal(`ValX):strengthVal(`Val0);// schedule if output value is differentif (out != outVal[evalElement])schedule(out);endendtask// Evaluate a D positive edge-triggered flip floptask evalDEdgeFF;input fanout; //first or second fanout indicator// check value change is on clock inputif (fanout ? (fo1TermNum[eventElement] = = 0):(fo0TermNum[eventElement] = = 0))begin// get old clock valueoldIn0 = log3(in0Val[evalElement]);storeInVal(fanout);in0 = log3(in0Val[evalElement]);// test for positive edge on clock inputif ((oldIn0 = = `Val0) &&(in0 = = `Val1))beginout = strength Val(log3(in1Val[evalElement]));if (out != outVal[evalElement])schedule(out);endendelsestoreInVal(fanout); // store data input valueendtask// Evaluate a wire with full strength valuestask evalWire;input fanout;reg [7:0] mask;beginstoreInVal(fanout);in0 = in0Val[evalElement];in1 = in1Val[evalElement];mask = getMask(in0[15:8]) & getMask(in0[7:0]) &getMask(in1[15:8]) & getMask(in1[7:0]);Switch Level Modelingout = fillBits((in0 | in1) & {mask, mask});if (out != outVal[evalElement])schedule(out);if(DebugFlags[2])display("in0 = %b_%b\nin1 = %b_%b\nmask= %b %b\nout = %b_%b",in0[15:8],in0[7:0],inl[15:8],in1[7:0],mask,mask, out[15:8],out[7:0]);endendtask// Given either a 0-strength or 1-strength half of a strength value// return a masking pattern for use in a wire evaluation.function [7:0] getMask;input [7:0] halfVal; //half a full strength valuecasez (halfVal)8'b???????l: getMask = 8'b11111111;8'b??????10: getMask = 8'b11111110;8'b?????100: getMask = 8'b11111100;8'b????1000: getMask = 8'b11111000;8'b???10000: getMask = 8'b11110000;8'b??100000: getMask = 8'b11100000;8'b?1000000: getMask = 8'b11000000;8'b10000000: getMask = 8'b10000000;8'b00000000: getMask = 8'b11111111;endcaseendfunction// Schedule the evaluation element to change to a new value.// If the element is already scheduled then just insert the new value.task schedule;input [15:0] newVal; // new value to change tobeginif(DebugFlags[0])display("Element %0d, type %0s, scheduled to change to %s(%b_%b)",evalElement, typeString(eleType[evalElement]),valString(newVal), newVal[l5:8], newVal[7:0]);if (! schedPresent[evalElement])beginschedList[evalElement] = nextList;schedPresent[evalElement] = 1;nextList = evalElement;end279The Verilog Hardware Description Language280outVal[evalElement] = newVal;endendtaskendmodule10.4.3 Simulation ResultsLoading toggle circuitLoading element 1, type DEdgeFF, with initial value 1(00000000_01000000)Loading element 2, type DEdgeFF, with initial value 1(00000000_01000000)Loading element 3, type Nand, with initial value 0(01000000_00000000)Loading element 4, type DEdgeFF, with initial value 1(00000000_01000000)Applying 2 clocks to input element 1At 1,0 Element 1, type DEdgeFF, changes to 0(01000000_00000000)At 2,0 Element 1, type DEdgeFF, changes to 1(00000000_01000000)At 2,1 Element 4, type DEdgeFF, changes to 0(01000000_00000000)At 2,2 Element 3, type Nand, changes to 1(00000000_01000000)At 3,0 Element 1, type DEdgeFF, changes to 0(01000000_00000000)At 4,0 Element 1, type DEdgeFF, changes to 1(00000000_01000000)At 4,1 Element 4, type DEdgeFF, changes to 1(00000000_01000000)At 4,2 Element 3, type Nand, changes to 0(01000000_00000000)Changing element 2 to value 0 and applying 1 clockAt 5,0 Element 1, type DEdgeFF, changes to 0(01000000_00000000)At 5,0 Element 2, type DEdgeFF, changes to 0(01000000_00000000)At 5,1 Element 3, type Nand, changes to 1(00000000_01000000)At 6,0 Element 1, type DEdgeFF, changes to 1(00000000_01000000)Loading open-collector and pullup circuitLoading element 1, type DEdgeFF, with initial value 1(00000000_01000000)Loading element 2, type DEdgeFF, with initial value 0(01000000_00000000)Loading element 3, type Nand, with initial value 0(01000000_00000000)Loading element 4, type Nand, with initial value Z(00000000_00000001)Loading element 5, type Wire, with initial value 0(01000000_00000000)Loading element 6, type DEdgeFF, with initial value 1(00000000_00100000)Loading element 7, type Wire, with initial value 0(01000000_00000000)Changing element 1 to value 0At 7,0 Element 1, type DEdgeFF, changes to 0(01000000_00000000)At 7,1 Element 3, type Nand, changes to Z(00000000_00000001)At 7,2 Element 5, type Wire, changes to Z(00000000_00000001)At 7,3 Element 7, type Wire, changes to 1(00000000_00100000)Changing element 2 to value 1At 8,0 Element 2, type DEdgeFF, changes to 1(00000000_01000000)At 8,1 Element 4, type Nand, changes to 0(01000000_00000000)At 8,2 Element 5, type Wire, changes to 0(01000000_00000000)At 8,3 Element 7, type Wire, changes to 0(01000000_00000000)Switch Level Modeling281Changing element 2 to value XAt 9,0 Element 2, type DEdgeFF, changes to X(01111111_01111111)At 9,1 Element 4, type Nand, changes to X(01111111_00000001)At 9,2 Element 5, type Wire, changes to X(01111111_00000001)At 9,3 Element 7, type Wire, changes to X(01111111_00111111)10.5 SummaryWe have seen in this chapter how strengths may be assigned to gate outputs andassign statements, and how logic values driven at these strengths may be propagatedthrough gates, driven on nets, and stored on trireg nets.
The chapter closed with abrief discussion of the miniSim, a simulator written in the Verilog language that demonstrates how the logic strengths are combined together. Following this, the wholeminiSim example was presented.10.6 Exercises10.1 Change the method of monitoring in Example 10.2 to that of strobing the signals 1 time unit before the positive edge of the phase1 clock. Do this in such away as to be independent of the absolute value of d, i.e.
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