Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 48
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Table 9.1 lists all of the shorthand specifications used in tables for userdefined primitives.data0101?*state:?::?::1::1:: ?:: ?:output0;1;1;1;-;-;Example 9.6 Edge -Sensitive BehaviorWith Shorthand Notation9.4 Mixed Level- and Edge-Sensitive PrimitivesIt is quite common to mix both level- and edge-sensitive behavior in a user-definedprimitive.
Consider the edge-sensitive JK flip flop with asynchronous clear and presetshown in Example 9.7User-Defined Primitives247In this example, the preset and clear inputs are level-sensitive. The preset sectionof the table specifies that when preset is zero and clear is one, the output will be one.Further, if there are any transitions (as specified by the “*”) on the preset input andclear and the internal state are all ones, then the output will be one. The clear sectionof the table makes a similar specification for the clear input.The table then specifies the normal clocking situations.
The first five lines specifythe normal JK operations of holding a value, setting a zero, setting a one, and toggling. The last line states that no change will occur on a falling edge of the clock.The j and k transition cases specify that if the clock is a one or zero, then a transition on either j or k will not change the output.Finally, we have the cases that reduce the pessimism of the example by specifyingoutputs for more situations. The first three lines include the full set of rising-edgecases, i.e. those clock edges including x. Following these, the next four lines make further specifications on when a negative edge including x occurs on the clock.
Finally,the specification for clock having the value x is given. In all of these “pessimism reducing” cases, we have specified no change to the output.There are times when an edge-sensitive and level-sensitive table entry will conflictwith each other. The general rule is that when the input and current state conditionsThe Veritog Hardware Description Language248primitive jkEdgeFF(output reg q,inputclock, j, k, preset, clear);table//clock jk pc// preset logic??? 01??? *1:?::1:1;1;// clear logic??? 10??? 1*:?::0:0;0;cases:?:?:?:0:1:?-;0;1;1;0;-;state output// normal clockingr00 11r01 11r10 11r11 11r11 11f?? ??//j and k transition casesb *? ??:?:b?* ??:?://cases reducing pessimismp00 11:?:p0? 1? :0:p?0 ?1 :1:(x0) ?? ?? :?:(1x) 00 11:?:(1x) 0? 1? :0:(1x) ?0 ?1:1:x *0 ?1:1:x 0* 1?:0:endtableendprimitive-;-;-;-;-;-;-;-;-;-;-;Example 9.7 AJK Flip FlopUser-Defined Primitives249of both a level-sensitive table row and an edge-sensitive table row specify conflictingnext-states, the level-sensitive entry will dominate the edge-sensitive entry.
Considerthe table entry in Example 9.7://clock jk pc??? 01state output:?:1;//Case Awhich includes the case:100 01:0:1;//Case B?? ??:?:-;//Case C00 01:0:0;//Case DAnother entry:fincludes the case:fCase B is a level-sensitive situation and case D is an edge-sensitive situation, but theydefine conflicting next state values for the same input combinations. In these twocases, the j, k, p, and c inputs are the same. Case B states that when the clock is oneand the state is zero, then the next state is one. However, case D states that whenthere is a one to zero transition on the clock and the state is zero, then the next state iszero. But for a falling edge to be on the clock with the other inputs as given, the clockmust just previously have been one and thus the next state should have alreadychanged to one, and not zero. In all cases, the level-sensitive specification dominatesand the next state will be one.9.5 SummaryThe user-defined primitives represent an advanced capability in the language forspecifying combinational and sequential logic primitives.
The specifications areefficient and compact and allow for the reduction of pessimism with respect to the xvalue.9.6 Exercises9.1 Write combinational user defined primitives that are equivalent to:A. the predefined 3-input XOR gate,B. the equation ~((a c & b) | (c & d)), and250The Verilog Hardware Description LanguageC. the multiplexor illustrated as follows:9.29.39.49.5Try to reduce pessimism in the multiplexor description when the select line isunknown.Try to reduce the pessimism in Example 9.4 for cases when the clock becomesunknown.
Can more entries in Example 9.5 be given to further reduce pessimism?Write a sequential user defined primitive of a simple two input positive edgetriggered toggle flip flop with an asynchronous clear input.Write a combinational user defined primitive of a strobed difference detector.The device is to have 3 inputs: inA, inB and strobe, such that when strobe is 1,inA is compared with inB. The output should be 0 when inA equals inB, and 1when the comparison fails. When inB is unknown this indicates a don’t-care situation such that regardless of the value of inA the output is a 0.Develop a gate level description of an edge-sensitive JK flip flop with asynchronous clear and preset, and compare it against the user defined primitive inExample 9.7 with respect to pessimism from the unknown value.10Switch LevelModelingDesigns at the logic level of abstraction, describe a digital circuit in terms of primitivelogic functions such as OR, and NOR, etc., and allow for the nets interconnecting thelogic functions to carry 0, 1, x and z values.
At the analog-transistor level of modeling,we use an electronic model of the circuit elements and allow for analog values of voltages or currents to represent logic values on the interconnections.The switch level of modeling provides a level of abstraction between the logic andanalog-transistor levels of abstraction, describing the interconnection of transmissiongates which are abstractions of individual MOS and CMOS transistors. The switch leveltransistors are modeled as being either on or off, conducting or not conducting. Further, the values carried by the interconnections are abstracted from the whole range ofanalog voltages or currents to a small number of discrete values. These values arereferred to as signal strengths.10.1 A Dynamic MOS Shift Register ExampleWe began our discussion of logic level modeling in Chapter 6 by listing the primitiveset of gates provided by the Verilog language (the list is reproduced as Table 10.1).252The Verilog Hardware Description LanguageAt the time, only the logic level primitives were discussed.
We can see from the switchlevel primitives, shown in the right three columns of the table, that they all modelindividual MOS/CMOS transistors.Figure 10.1 illustrates the differences in modeling at the switch and logic levels.The circuit is a three stage, inverting shift register controlled by two phases of a clock.The relative timing of the clock phases is also shown in the figure.
The Verilogdescription is shown in Example 10.1.Switch Level Modeling253module shreg/* IO port declarations, where 'out' is the inverseof 'in' controlled by the dual-phased clock */(output tri out,//shift register outputinputin,//shift register inputphase1,//clocksphase2);triwb1, wb2;//tri nets pulled up to VDDpullup (wb1), (wb2), (out);//depletion mode pullup devicestrireg(medium) wa1, wa2, wa3; //charge storage nodessupply0nmos #3gnd;//ground supply//pass devices and their interconnectionsa1(wa1, in, phase1), b1(wb1, gnd, wa1),a2(wa2, wb1, phase2), b2(wb2, gnd, wa2),a3(wa3, wb2, phase1), gout(out, gnd, wa3);endmoduleExample 10.1 MOS Shift RegisterThe circuit consists only of nmos transistors and depletion mode pullup transistorsinterconnected by nets of type tri and trireg. tri nets model tristate nets. In this example, tri nets wb1, wb2, and out are pulled up to VDD through the declaration of threeunnamed pullup gates.Three trireg nets, wa1, wa2, and wa3, are declared.
Trireg nets are different fromother types of nets in that they store a value when all gates driving the net have turnedoff. That is, a driver can drive them (i.e. charge them) and then turn off. The valuedriven will remain on the trireg net even though it is no longer being driven. Thesenets are used in this example to model the dynamic storage of the shift register stages.The declaration of the nets shows them being given the medium capacitor strength(which also happens to be the default).A net of type supply0 is defined and named gnd, modeling a connection to theground terminal of the power supply.
Finally, the nmos pass transistors are instantiated and connected, completing the shift register definition.It is instructive to evoke the inputs to the shift register model and follow its simulation output. The module in Example 10.2 instantiates a copy of the shreg moduleThe Verilog Hardware Description Language254module waveShReg;wireshiftout;//net to receive circuit output valueregshiftin;//register to drive value into circuitreg phase1, phase2; //clock driving valuesparametershregd = 100; //define the waveform time stepcct (shiftout, shiftin, phase1, phase2);initialbegin :mainshiftin = 0; //initialize waveform input stimulusphase1 = 0;phase2 = 0;setmon;// setup the monitoring informationrepeat(2)//shift data inclockcct;endtask setmon;begin//display header and setup monitoringtime clks in out wa1-3 wb1-2");phase1, phase2,,,,,,shiftin,,,, shiftout,,,,,cct.wa1, cct.wa2, cct.wa3,,,,,cct.wb1, cct.wb2);endendtasktask clockcct; //produce dual-phased clock pulsebegin#d phase1 = 1; //time step defined by parameter d#d phase1 = 0;#d phase2 = 1;#d phase2 = 0;endendtaskendmoduleExample 10.2 Simulating the MOS Shift Registerdescribed in Example 10.1, drives its inputs and monitors its outputs.
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