Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition (798541), страница 65
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All rights reservedThe Verilog Hardware Description Language372variable_identifier ::= identifierG.10.4 Identifier branchessimple_hierarchical_branch<Superscript>3 ::=simple_identifier [ [ unsigned_number ] ][ { simple_identifier [ [ unsigned_number ] ] } ]escaped_hierarchical_branch<Superscript>4::=escaped_identifier [ [ unsigned_number ] ][ { escaped_identifier [ [ unsigned_number ] ] } ]G.10.5 White spacewhite_space ::= space tab | newline | eof<Superscript>6NOTES1)2)3)4)5)6)Embedded spaces are illegal.A simple_identifier and arrayed_reference shall start with an alpha orunderscore (_) character, shall have at least one character, and shall nothave any spaces.Theperiod(.)insimple_hierarchical_identifierandsimple_hierarchical_branch shall not be preceded or followed by white_space.The period in escaped_hierarchical_identifier and escaped_hierarchical_branch shall be preceded by white_space, but shall not be followed bywhite_space.The$characterinasystem_function_identifierorsystem_task_identifier shall not be followed by white_space.
Asystem_function_identifier or system_task_identifier shall not beescaped.End of file.IEEE Std 1364-2001, Copyright © 2001, IEEE. All rights reservedSymbolsAOperator symbolsSee also operator table 315! 80!= 76,79!== 79# 183$ 312$display system task 124,168, 333See also display system task$fclose system task 335$fdisplay system task 335$finish system task 336$fmonitor system task 335$fopen system task 335$fstrobe system task 335$fwrite system task 335$monitor system task 334example of 4, 9, 254, 302$random system task 168, 170, 336See also random system task$readmemb system task 337$readmemh system task 124, 337$signed 319$stime 336$stop system task 336$strobe system task 335$time 336$unsigned 319$write system task 333&& 80<< 76, 82<= 79== 79=== 79114> 79>= 79>> 94? 242?: 81@ 112\ 312\" 312\ddd 312\n 312\t 312`default-net type 163`define 75, 124, 266`timescale 22, 185|| 80~ 317always 74contrast with initial 75formal definition 74in behavioral synthesis 198in synthesis 11, 40input set 198internal register set 198output set 199process definition 74and&, &&, See table of operators 315See gate types 323arithmetic laws 79array of instancesexample 150assignformal definition 172, 259keyword 172assignmentscontinuous 158, 171contrasting blocking and nonblocking 189, 229non-blocking 17, 19, 131, 226procedural 74procedural continuous 136attributes 44Bbegin-end blocksdisabling 132example of 76fork-join 138formal definition 139formal definition 133named 85sequential 138formal definition 139behavioral modeling 73clock event 196combinational logic 11contrasting assignments 189cycle-accurate specification 195, 198finite state machines (FSM) 15FSM-Datapath 58Mealy/Moore 203pipeline processor 131sequential circuits 14behavioral synthesis 198always 198cycle-accurate specification 198Mealy/Moore 203substeps 209374bidirectional gates 328bit widthof expressions 322See part-selectbit-select 78, 165, 330, 342example of 16, 23, 87formal definition 78bitwise negation (~) 317See also logical negation 317black holes 221string theory 311block declarations 133See also begin-end blocksbufSee gate types 325bufif0See gate types 326bufiflSee gate types 326Ccasecasex 90casez 90contrast to if-else-if 89default action 88formal definition 87full 44keyword 86parallel 45synthesizable 43case equality operator (= = =) 79case inequality operator (!= =) 79casexSee casecasezSee casecharge decay 183, 255, 260clock event 196combinational logicbehavioral modeling 11synthesis of 37, 40synthesizable specification 11comments 309compiler directivesdefault-net type 163define 75, 266timescale 22, 185concatenation 167example of 24, 94formal definition 95conditional operator (?:) 81formal definition 81constants 310The Verilog Hardware Description Languagecontinuous assignment 158, 171example of 38formal definition 172on to nets 174synthesis 38with function call 173control path 41, 48cycle-accurate specification 195, 198Mealy/Moore 203Ddeassignkeyword 137declarationsimplicit 163defaultaction in case 88formal definition 88definecompiler directive 75, 266definitions.
See formal definitiondefparamkeyword 149See also parametersdelayformal definition 183delay modeling 180across a module 187bidirectional gates 328charge decay 183, 255, 260edge specification 184example of 181formal definition 183full connection 188inertial 212min, typical, max 186parallel connection 188path declarations 187six values 188disable 132formal definition 85display system task 124, 168, 333example of 79, 254example with strengths 257Eedge sensitive 50comparison to level sensitive 121example of negedge 126formal definition 112non-blocking assignment 19positive edge 121synthesis of flip flops 50375user-defined primitives 244See also event controledge specificationdelay modeling 184elseformal definition 80endSee begin-end blocksendcaseSee caseendfunctionSee functionsendmoduleSee moduleendspecifySee specifyendtaskSee taskequal operator 79comparison with case equality 79not equal operatorcomparison with case inequality 79evaluation event 216event 211evaluation 216update 216event control 111, 113contrast to wait 121definition of an edge 113edge specification 112event control statements 111example of 112, 115formal definition 112named events 114or-ing events 12event list 215event triggerformal definition 114event-driven simulation 214examplesAND of complements 164array of instances 150behavioral reset 202behavioral synthesisspecification 196break 85buffer-driver 175carry 240clock generator 22compare modules 61continue 85continuous assign 60continuous assignment 61counter-display module 26cycle-accurate specification 196display driver — behavioral 12display driver simulator 4display driver structure 2display driver with ports 7don’t care in specification 45D-type edge triggered flip-flop 187four-bit counter 21FSM and Datapath 62full adder 159Hamming encode/decode 168I/O buffer 186implicit FSM 56inferred flip flop 50inferred latch 42, 49input, output, internal sets 198intra-assignment delay 232intra-assignment repeat 233introductory module 2JK edge triggered flip-flop 248latch 244logical don’t care 44, 45michael and lisa not doing it 232microprocessor reset 138microprocessor with fork-join 138mini simulator 265mixed behavior and structure 26MOS shift register 253MOS shift register output 254MOS static RAM 257multiplexor 173multiply as separate module 101multiply function 98multiply task 94named begin-end block 85non-blocking assignment 20, 228,232, 233non-determinism 222one-bit full adder 171or in event control 12overlap in timing models 214pipeline processor 131pipelined multiplier 233procedural continuous assign 137resolving 0, 1, x from strengths 266scope and hierarchical names 104simple computer 87, 88, 91specification for behavioralsynthesis 204synchronous bus (behavioral andstructural modeling) 177synchronous bus (behavioralmodel) 124synthesizable adder 60376The Verilog Hardware Description Languagesynthesizable always 40, 41, 42synthesizable assign 38synthesizable case 43synthesizable flip flop 51synthesizable FSM 16, 20, 55, 228synthesizable gate primitives 37synthesizable loops 47synthesizable register 60time out 113top-level module 23tristate latch 181tri-state synthesis 52twoPhiLatch 218why #0 225wire concatenation 24xor module 174explicit FSM style 53expressionsigned 319unsigned 319Ffclose system task 335fdisplay system task 335finish system task 336flip flop inferences 50fmonitor system task 335fopen system task 335for loopformal definition 83foreverexample of 84how long is it? 85fork-join blocks 138See also begin-end blocksformal definition 339–??always 74assign 172, 259begin-end blocks 133, 139bit-select 78case 87concatenation 95conditional operator (?:) 81default 88delay (#) 183else 80event control (@) 112event triggering ( ) 114for 83fork-join 139function 97function call 99gate instantiation 159, 259initial 74module 146module instantiation 148named block 139negedge 112nets 165, 174,260non-blocking assignment 231parameters 146part-select 78port 342posedge 112procedural continuous assign 137repeat 83strength 260task 93task enable 96user-defined primitives 241wait 117while 83FSM-D 58fstrobe system task 335full case 44functions 91, 97automtic 99constant 99contrast procedural vs.continuous 173contrast to tasks 92, 97example of 98formal definition 97formal definition of call 99a structural view 100fwrite system task 335Ggate instantiationarray of instances 150formal definition 159, 259synthesis 37gate level modeling 158bidirectional gates 328gate primitives 158multi-value truth tables 323table of gate primitives 161See also user-defined primitivesgate level timing model 158, 212generate blocks 151ground connectionexample of 253HH value 182, 327handshake 117Hi abbreviation 259377hierarchical names 102, 105, 114example 104example of 149Hierarchical naming 149hierarchyspecifying 21high impedance 162, 259highz 259highz0 259highzl 259II/O system functions 337identifiers 312keywords 313scope 102system 312ifambiguous (x,z) values 77else clause 75example of 76keyword 75if-else-if 86contrast to case 89example of 87implicit declarations 163implicit FSM 56inertial delay 212, 232inferred 42example of latch 42flip flops 50latch 42, 48sequential elements 48tri-state 52initialcontrast with always 75formal definition 74inoutdefinition 144example in task 94port type 144use of 175input 21, 23, 26, 144input set 40, 198instantiationSee gate instantiationSee module instantiationintegers 329, 331intra-assignment delay 112, 134, 222,226, 231Kkeywordslist of 313LLvalue 182, 327La abbreviation 259large 259, 260large capacitor 259level sensitive 48, 116, 121, 244lexical conventions 309Local parameters 147logic values 162logical expressionsin conditional expressions 80logical negation (!) 316example of 76, 80, 82See also bitwise negation 316loopsexit from 85in synthesis 46See disableSee forSee foreverSee repeatSee whileMMe abbreviation 259medium 259, 260medium capacitor 259memory 329, 330example of 87multidimensional 331moduleconnection by port names 144formal definition 146introductory example 2keyword 143parameter override 147port specifications 143module instantiationarray of instances 150formal definition 148monitor system task 79, 334example of 4, 9, 254, 302multi-way branchingif-else-if case 86Nnamed begin-end blocksformal definition 139named event 113See also event controlnames 312378hierarchical 102, 114keywords 313scope 102system 312nandSee gate types 324negative edge 126negedgeformal definition 112See also edge sensitive 126net typestable of 166nets 158, 163, 174contrast wire and wand 164delay specification 174formal definition 165, 174, 260implicit declarations 163table of types 166trireg 255trireg charge decay 183, 255, 260wire 163nmos switch level primitiveexample of 253See gate types 327non-blocking assignment 17, 19, 131,226non-determinism 220interleaved statements 224norSee gate types 324notSee gate types 325not equal operator 79notif0See gate types 326notif1See gate types 327number specification 310Ooperators 310bit width of results 322multi-valued truth tables 321precedence 320table of 315orI, I I, See table of operators 315in event control 12primitive logic gate 324See gate types 324output 21, 23, 26, 144output set 199The Verilog Hardware Description LanguagePparallel blocks (fork-join) 138See also begin-end blocksparallel case 45Parameters 146local parameters 147parametersdefparam 149example of 55, 60, 174formal definition 146as module generics 147part-select 78, 165, 330example of 76, 82, 95, 167formal definition 78pmos switch level primitivesSee gate types 327posedgeformal definition 112See also edge sensitive 121precedence of operators 320procedural continuous assign 136deassign 137example of 137formal definition 137See also assignmentsprocedural timing model 74, 213process concept 73, 109, 173execution model 74, 211compared tocontinuousassign 74comparedtogateprimitives 74interleaved statements 224non-determinism 220procedural timing model 74, 213zero-time 220process model 198producer-consumer handshake 117Pu abbreviation 259pull 259pull drive 259pull0 256pulll 256pulldown switch level primitiveSee gate types 328pullup switch level primitiveexample of 253See gate types 328Qquasi-continuous assign.
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