Volume 1 Basic Architecture (794100), страница 85
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With the divide-by-zero andprecision exceptions masked, the processor will produce the correct result. FDIV ofR1 into 1 gives infinity, and then FDIV of (infinity +R2 +R3) into 1 gives zero.R1R2Equivalent Resistance =R31111++R1R3R2Figure D-4. Arithmetic Example Using InfinityBy masking or unmasking specific numeric exceptions in the x87 FPU control word,programmers can delegate responsibility for most exceptions to the processor,reserving the most severe exceptions for programmed exception handlers.
Exception-handling software is often difficult to write, and the masked responses havebeen tailored to deliver the most reasonable result for each condition. For themajority of applications, masking all exceptions yields satisfactory results with theVol. 1 D-13GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSleast programming effort. Certain exceptions can usefully be left unmasked duringthe debugging phase of software development, and then masked when the cleansoftware is actually run. An invalid-operation exception for example, typically indicates a program error that must be corrected.The exception flags in the x87 FPU status word provide a cumulative record of exceptions that have occurred since these flags were last cleared. Once set, these flags canbe cleared only by executing the FCLEX/FNCLEX (clear exceptions) instruction, byreinitializing the x87 FPU with FINIT/FNINIT or FSAVE/FNSAVE, or by overwriting theflags with an FRSTOR or FLDENV instruction.
This allows a programmer to mask allexceptions, run a calculation, and then inspect the status word to see if any exceptions were detected at any point in the calculation.D.3.2.2Software Exception HandlingIf the x87 FPU in or with an IA-32 processor (Intel 286 and onwards) encounters anunmasked exception condition, with the system operated in the MS-DOS compatibility mode and with IGNNE# not asserted, a software exception handler is invokedthrough a PIC and the processor’s INTR pin.
The FERR# (or ERROR#) output fromthe x87 FPU that begins the process of invoking the exception handler may occurwhen the error condition is first detected, or when the processor encounters the nextWAIT or x87 FPU instruction. Which of these two cases occurs depends on theprocessor generation and also on which exception and which x87 FPU instruction triggered it, as discussed earlier in Section D.1, “MS-DOS Compatibility Sub-mode forHandling x87 FPU Exceptions,” and Section D.2, “Implementation of the MS-DOSCompatibility Sub-mode in the Intel486, Pentium, and P6 Processor Family, andPentium 4 Processors.” The elapsed time between the initial error signal and the invocation of the x87 FPU exception handler depends of course on the external hardwareinterface, and also on whether the external interrupt for x87 FPU errors is enabled.But the architecture ensures that the handler will be invoked before execution of thenext WAIT or floating-point instruction since an unmasked floating-point exceptioncauses the processor to freeze just before executing such an instruction (unless theIGNNE# input is active, or it is a no-wait x87 FPU instruction).The frozen processor waits for an external interrupt, which must be supplied byexternal hardware in response to the FERR# (or ERROR#) output of the processor(or coprocessor), usually through IRQ13 on the “slave” PIC, and then through INTR.Then the external interrupt invokes the exception handling routine.
Note that if theexternal interrupt for x87 FPU errors is disabled when the processor executes an x87FPU instruction, the processor will freeze until some other (enabled) interrupt occursif an unmasked x87 FPU exception condition is in effect. If NE = 0 but the IGNNE#input is active, the processor disregards the exception and continues. Error reportingvia an external interrupt is supported for MS-DOS compatibility.
Chapter 17, “IA-32Architecture Compatibility,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, contains further discussion of compatibility issues.The references above to the ERROR# output from the x87 FPU apply to the Intel 387and Intel 287 math coprocessors (NPX chips). If one of these coprocessors encounters an unmasked exception condition, it signals the exception to the Intel 286 orD-14 Vol.
1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSIntel386 processor using the ERROR# status line between the processor and thecoprocessor. See Section D.1, “MS-DOS Compatibility Sub-mode for Handling x87FPU Exceptions,” in this appendix, and Chapter 17, “IA-32 Architecture Compatibility,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 3A, for differences in x87 FPU exception handling.The exception-handling routine is normally a part of the systems software. Theroutine must clear (or disable) the active exception flags in the x87 FPU status wordbefore executing any floating-point instructions that cannot complete executionwhen there is a pending floating-point exception.
Otherwise, the floating-pointinstruction will trigger the x87 FPU interrupt again, and the system will be caught inan endless loop of nested floating-point exceptions, and hang. In any event, theroutine must clear (or disable) the active exception flags in the x87 FPU status wordafter handling them, and before IRET(D). Typical exception responses may include:••Incrementing an exception counter for later display or printing.•Aborting further execution, or using the exception pointers to build an instructionthat will run without exception and executing it.Printing or displaying diagnostic information (e.g., the x87 FPU environment andregisters).Applications programmers should consult their operating system's referencemanuals for the appropriate system response to numerical exceptions.
For systemsprogrammers, some details on writing software exception handlers are provided inChapter 5, “Interrupt and Exception Handling,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, as well as in Section D.3.4, “x87 FPUException Handling Examples,” in this appendix.As discussed in Section D.2.1.2, “Recommended External Hardware to Support theMS-DOS Compatibility Sub-mode,” some early FERR# to INTR hardware interfaceimplementations are less robust than the recommended circuit. This is because theydepended on the exception handler to clear the x87 FPU exception interrupt requestto the PIC (by accessing port 0F0H) before the handler causes FERR# to be deasserted by clearing the exception from the x87 FPU itself. To eliminate the chance ofa problem with this early hardware, Intel recommends that x87 FPU exceptionhandlers always access port 0F0H before clearing the error condition from the x87FPU.D.3.3Synchronization Required for Use of x87 FPU ExceptionHandlersConcurrency or synchronization management requires a check for exceptions beforeletting the processor change a value just used by the x87 FPU.
It is important toremember that almost any numeric instruction can, under the wrong circumstances,produce a numeric exception.Vol. 1 D-15GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSD.3.3.1Exception Synchronization: What, Why and WhenException synchronization means that the exception handler inspects and deals withthe exception in the context in which it occurred.
If concurrent execution is allowed,the state of the processor when it recognizes the exception is often not in the contextin which it occurred. The processor may have changed many of its internal registersand be executing a totally different program by the time the exception occurs. If theexception handler cannot recapture the original context, it cannot reliably determinethe cause of the exception or recover successfully from the exception. To handle thissituation, the x87 FPU has special registers updated at the start of each numericinstruction to describe the state of the numeric program when the failed instructionwas attempted.This provides tools to help the exception handler recapture the original context, butthe application code must also be written with synchronization in mind. Overall,exception synchronization must ensure that the x87 FPU and other relevant parts ofthe context are in a well defined state when the handler is invoked after an unmaskednumeric exception occurs.When the x87 FPU signals an unmasked exception condition, it is requesting help.The fact that the exception was unmasked indicates that further numeric programexecution under the arithmetic and programming rules of the x87 FPU will probablyyield invalid results.
Thus the exception must be handled, and with proper synchronization, or the program will not operate reliably.For programmers using higher-level languages, all required synchronization is automatically provided by the appropriate compiler. However, for assembly languageprogrammers exception synchronization remains the responsibility of theprogrammer. It is not uncommon for a programmer to expect that their numericprogram will not cause numeric exceptions after it has been tested and debugged,but in a different system or numeric environment, exceptions may occur regularlynonetheless. An obvious example would be use of the program with some numbersbeyond the range for which it was designed and tested.
Example D-1 and ExampleD-2 in Section D.3.3.2, “Exception Synchronization Examples,” show a subtle way inwhich unexpected exceptions can occur.As described in Section D.3.1, “Floating-Point Exceptions and Their Defaults,”depending on options determined by the software system designer, the processorcan perform one of two possible courses of action when a numeric exception occurs.•The x87 FPU can provide a default fix-up for selected numeric exceptions. If thex87 FPU performs its default action for all exceptions, then the need for exceptionsynchronization is not manifest.
However, code is often ported to contexts andoperating systems for which it was not originally designed. Example D-1 andExample D-2, below, illustrate that it is safest to always consider exceptionsynchronization when designing code that uses the x87 FPU.D-16 Vol. 1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS•Alternatively, a software exception handler can be invoked to handle theexception. When a numeric exception is unmasked and the exception occurs, thex87 FPU stops further execution of the numeric instruction and causes a branchto a software exception handler.
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