Volume 1 Basic Architecture (794100), страница 82
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The accompanying interrupt vectornumber could then be used to access the floating-point exception handler.However, the original IBM* PC design and MS-DOS operating system used a differentmechanism for handling the INT output from the 8087. It connected the INT pindirectly to the NMI input pin of the 8086 or 8088. The NMI interrupt handler then hadto determine if the interrupt was caused by a floating-point exception or another NMIevent. This mechanism is the origin of what is now called the “MS-DOS compatibilitymode.” The decision to use this latter floating-point exception handling mechanismcame about because when the IBM PC was first designed, the 8087 was not available.When the 8087 did become available, other functions had already been assigned tothe eight inputs to the PIC. One of these functions was a BIOS video interrupt, whichwas assigned to interrupt number 16 for the 8086 and 8088.The Intel 286 processor created the “native mode” for handling floating-point exceptions by providing a dedicated input pin (ERROR#) for receiving floating-point exception signals and a dedicated interrupt number, 16.
Interrupt 16 was used to signalfloating-point errors (also called math faults). It was intended that the ERROR# pinon the Intel 286 be connected to a corresponding ERROR# pin on the Intel 287numeric coprocessor. When the Intel 287 signals a floating-point exception using thismechanism, the Intel 286 generates an interrupt 16, to invoke the floating-pointexception handler.To maintain compatibility with existing PC software, the native floating-point exception handling mode of the Intel 286 and 287 was not used in the IBM PC AT systemdesign.
Instead, the ERROR# pin on the Intel 286 was tied permanently high, andthe ERROR# pin from the Intel 287 was routed to a second (cascaded) PIC. Theresulting output of this PIC was routed through an exception handler and eventuallycaused an interrupt 2 (NMI interrupt). Here the NMI interrupt was shared with IBMPC AT’s new parity checking feature. Interrupt 16 remained assigned to the BIOSvideo interrupt handler.
The external hardware for the MS-DOS compatibility modemust prevent the Intel 286 processor from executing past the next x87 FPU instruction when an unmasked exception has been generated. To do this, it asserts theBUSY# signal into the Intel 286 when the ERROR# signal is asserted by the Intel 287.The Intel386 processor and its companion Intel 387 numeric coprocessor providedthe same hardware mechanism for signaling and handling floating-point exceptionsas the Intel 286 and 287 processors. And again, to maintain compatibility withexisting MS-DOS software, basically the same MS-DOS compatibility floating-pointexception handling mechanism that was used in the IBM PC AT was used in PCs basedon the Intel386 processor.D-2 Vol. 1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSD.2IMPLEMENTATION OF THE MS-DOS COMPATIBILITYSUB-MODE IN THE INTEL486, PENTIUM, AND P6PROCESSOR FAMILY, AND PENTIUM 4 PROCESSORSBeginning with the Intel486 processor, the IA-32 architecture provided a dedicatedmechanism for enabling the MS-DOS compatibility mode for x87 FPU exceptions andfor generating external x87 FPU-exception signals while operating in this mode.
Thefollowing sections describe the implementation of the MS-DOS compatibility mode inthe Intel486 and Pentium processors and in the P6 family and Pentium 4 processors.Also described is the recommended external hardware to support this mode of operation.D.2.1MS-DOS Compatibility Sub-mode in the Intel486 andPentium ProcessorsIn the Intel486 processor, several things were done to enhance and speed up thenumeric coprocessor, now called the floating-point unit (x87 FPU).
The most important enhancement was that the x87 FPU was included in the same chip as theprocessor, for increased speed in x87 FPU computations and reduced latency for x87FPU exception handling. Also, for the first time, the MS-DOS compatibility mode wasbuilt into the chip design, with the addition of the NE bit in control register CR0 andthe addition of the FERR# (Floating-point ERRor) and IGNNE# (IGNore NumericError) pins.The NE bit selects the native x87 FPU exception handling mode (NE = 1) or theMS-DOS compatibility mode (NE = 0). When native mode is selected, all signaling offloating-point exceptions is handled internally in the Intel486 chip, resulting in thegeneration of an interrupt 16.When MS-DOS compatibility mode is selected, the FERRR# and IGNNE# pins areused to signal floating-point exceptions.
The FERR# output pin, which replaces theERROR# pin from the previous generations of IA-32 numeric coprocessors, isconnected to a PIC. A new input signal, IGNNE#, is provided to allow the x87 FPUexception handler to execute x87 FPU instructions, if desired, without first clearingthe error condition and without triggering the interrupt a second time. This IGNNE#feature is needed to replicate the capability that was provided on MS-DOS compatible Intel 286 and Intel 287 and Intel386 and Intel 387 systems by turning off theBUSY# signal, when inside the x87 FPU exception handler, before clearing the errorcondition.Note that Intel, in order to provide Intel486 processors for market segments that hadno need for an x87 FPU, created the “SX” versions.
These Intel486 SX processors didnot contain the floating-point unit. Intel also produced Intel 487 SX processors forend users who later decided to upgrade to a system with an x87 FPU. These Intel 487SX processors are similar to standard Intel486 processors with a working x87 FPU onboard.Vol. 1 D-3GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSThus, the external circuitry necessary to support the MS-DOS compatibility mode forIntel 487 SX processors is the same as for standard Intel486 DX processors.The Pentium, P6 family, and Pentium 4 processors offer the same mechanism (the NEbit and the FERR# and IGNNE# pins) as the Intel486 processors for generating x87FPU exceptions in MS-DOS compatibility mode.
The actions of these mechanisms areslightly different and more straightforward for the P6 family and Pentium 4 processors, as described in Section D.2.2, “MS-DOS Compatibility Sub-mode in the P6Family and Pentium 4 Processors.”For Pentium, P6 family, and Pentium 4 processors, it is important to note that thespecial DP (Dual Processing) mode for Pentium processors and also the more generalIntel MultiProcessor Specification for systems with multiple Pentium, P6 family, orPentium 4 processors support x87 FPU exception handling only in the native mode.Intel does not recommend using the MS-DOS compatibility x87 FPU mode forsystems using more than one processor.D.2.1.1Basic Rules: When FERR# Is GeneratedWhen MS-DOS compatibility mode is enabled for the Intel486 or Pentium processors(NE bit is set to 0) and the IGNNE# input pin is de-asserted, the FERR# signal isgenerated as follows:1. When an x87 FPU instruction causes an unmasked x87 FPU exception, theprocessor (in most cases) uses a “deferred” method of reporting the error.
Thismeans that the processor does not respond immediately, but rather freezes justbefore executing the next WAIT or x87 FPU instruction (except for “no-wait”instructions, which the x87 FPU executes regardless of an error condition).2. When the processor freezes, it also asserts the FERR# output.3. The frozen processor waits for an external interrupt, which must be supplied byexternal hardware in response to the FERR# assertion.4.
In MS-DOS compatibility systems, FERR# is fed to the IRQ13 input in thecascaded PIC. The PIC generates interrupt 75H, which then branches to interrupt2, as described earlier in this appendix for systems using the Intel 286 and Intel287 or Intel386 and Intel 387 processors.The deferred method of error reporting is used for all exceptions caused by the basicarithmetic instructions (including FADD, FSUB, FMUL, FDIV, FSQRT, FCOM andFUCOM), for precision exceptions caused by all types of x87 FPU instructions, and fornumeric underflow and overflow exceptions caused by all types of x87 FPU instructions except stores to memory.Some x87 FPU instructions with some x87 FPU exceptions use an “immediate”method of reporting errors.
Here, the FERR# is asserted immediately, at the timethat the exception occurs. The immediate method of error reporting is used for x87FPU stack fault, invalid operation and denormal exceptions caused by all transcendental instructions, FSCALE, FXTRACT, FPREM and others, and all exceptions (exceptprecision) when caused by x87 FPU store instructions. Like deferred error reporting,D-4 Vol. 1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSimmediate error reporting will cause the processor to freeze just before executingthe next WAIT or x87 FPU instruction if the error condition has not been cleared bythat time.Note that in general, whether deferred or immediate error reporting is used for anx87 FPU exception depends both on which exception occurred and which instructioncaused that exception.
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