Volume 1 Basic Architecture (794100), страница 84
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First,the first floating-point error condition could be of the “immediate” category (asdefined in Section D.2.1.1, “Basic Rules: When FERR# Is Generated”) that assertsFERR# immediately. If the system delay before asserting INTR is long enough, relative to the time elapsed before the no-wait floating-point instruction, INTR can beasserted inside the interrupt window for the latter. Second, consider two no-wait x87FPU instructions in close sequence, and assume that a previous x87 FPU instructionhas caused an unmasked numeric exception. Then if the INTR timing is too long foran FERR# signal triggered by the first no-wait instruction to hit the first instruction’sinterrupt window, it could catch the interrupt window of the second.The possible malfunction of a no-wait x87 FPU instruction explained above cannothappen if the instruction is being used in the manner for which Intel originallydesigned it.
The no-wait instructions were intended to be used inside the x87 FPUexception handler, to allow manipulation of the x87 FPU before the error condition iscleared, without hanging the processor because of the x87 FPU error condition, andwithout the need to assert IGNNE#. They will perform this function correctly, sincebefore the error condition is cleared, the assertion of FERR# that caused the x87 FPUerror handler to be invoked is still active. Thus the logic that would assert FERR#briefly at a no-wait instruction causes no change since FERR# is already asserted.The no-wait instructions may also be used without problem in the handler after theerror condition is cleared, since now they will not cause FERR# to be asserted at all.If a no-wait instruction is used outside of the x87 FPU exception handler, it maymalfunction as explained above, depending on the details of the hardware interfaceimplementation and which particular processor is involved.
The actual interruptinside the window in the no-wait instruction may be blocked by surrounding it withthe instructions: PUSHFD, CLI, no-wait, then POPFD. (CLI blocks interrupts, and thepush and pop of flags preserves and restores the original value of the interrupt flag.)However, if FERR# was triggered by the no-wait, its latched value and the PICresponse will still be in effect.
Further code can be used to check for and correct sucha condition, if needed. Section D.3.6, “Considerations When x87 FPU SharedBetween Tasks,” discusses an important example of this type of problem and gives asolution.D.2.2MS-DOS Compatibility Sub-mode in the P6 Familyand Pentium 4 ProcessorsWhen bit NE = 0 in CR0, the MS-DOS compatibility mode of the P6 family andPentium 4 processors provides FERR# and IGNNE# functionality that is almost identical to the Intel486 and Pentium processors. The same external hardware describedin Section D.2.1.2, “Recommended External Hardware to Support the MS-DOSCompatibility Sub-mode,” is recommended for the P6 family and Pentium 4 processors as well as the two previous generations.
The only change to MS-DOS compatibility x87 FPU exception handling with the P6 family and Pentium 4 processors is thatall exceptions for all x87 FPU instructions cause immediate error reporting. That is,D-10 Vol. 1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSFERR# is asserted as soon as the x87 FPU detects an unmasked exception; there areno cases in which error reporting is deferred to the next x87 FPU or WAIT instruction.(As is discussed in Section D.2.1.1, “Basic Rules: When FERR# Is Generated,” mostexception cases in the Intel486 and Pentium processors are of the deferred type.)Although FERR# is asserted immediately upon detection of an unmasked x87 FPUerror, this certainly does not mean that the requested interrupt will always beserviced before the next instruction in the code sequence is executed.
To begin with,the P6 family and Pentium 4 processors execute several instructions simultaneously.There also will be a delay, which depends on the external hardware implementation,between the FERR# assertion from the processor and the responding INTR assertionto the processor. Further, the interrupt request to the PICs (IRQ13) may be temporarily blocked by the operating system, or delayed by higher priority interrupts, andprocessor response to INTR itself is blocked if the operating system has cleared theIF bit in EFLAGS.
Note that Streaming SIMD Extensions numeric exceptions will notcause assertion of FERR# (independent of the value of CR0.NE). In addition, theyignore the assertion/deassertion of IGNNE#).However, just as with the Intel486 and Pentium processors, if the IGNNE# input isinactive, a floating-point exception which occurred in the previous x87 FPU instruction and is unmasked causes the processor to freeze immediately when encounteringthe next WAIT or x87 FPU instruction (except for no-wait instructions).
This meansthat if the x87 FPU exception handler has not already been invoked due to the earlierexception (and therefore, the handler not has cleared that exception state from thex87 FPU), the processor is forced to wait for the handler to be invoked and handle theexception, before the processor can execute another WAIT or x87 FPU instruction.As explained in Section D.2.1.3, “No-Wait x87 FPU Instructions Can Get x87 FPUInterrupt in Window,” if a no-wait instruction is used outside of the x87 FPU exceptionhandler, in the Intel486 and Pentium processors, it may accept an unmasked exception from a previous x87 FPU instruction which happens to fall within the externalinterrupt sampling window that is opened near the beginning of execution of all x87FPU instructions. This will not happen in the P6 family and Pentium 4 processors,because this sampling window has been removed from the no-wait group of x87 FPUinstructions.D.3RECOMMENDED PROTOCOL FOR MS-DOS*COMPATIBILITY HANDLERSThe activities of numeric programs can be split into two major areas: program controland arithmetic.
The program control part performs activities such as deciding whatfunctions to perform, calculating addresses of numeric operands, and loop control.The arithmetic part simply adds, subtracts, multiplies, and performs other operationson the numeric operands. The processor is designed to handle these two parts separately and efficiently.
An x87 FPU exception handler, if a system chooses to implement one, is often one of the most complicated parts of the program control code.Vol. 1 D-11GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSD.3.1Floating-Point Exceptions and Their DefaultsThe x87 FPU can recognize six classes of floating-point exception conditions whileexecuting floating-point instructions:1. #I — Invalid operation#IS — Stack fault#IA — IEEE standard invalid operation2.
#Z — Divide-by-zero3. #D — Denormalized operand4. #O — Numeric overflow5. #U — Numeric underflow6. #P — Inexact result (precision)For complete details on these exceptions and their defaults, see Section 8.4, “x87FPU Floating-Point Exception Handling,” and Section 8.5, “x87 FPU Floating-PointException Conditions.”D.3.2Two Options for Handling Numeric ExceptionsDepending on options determined by the software system designer, the processortakes one of two possible courses of action when a numeric exception occurs:1. The x87 FPU can handle selected exceptions itself, producing a default fix-up thatis reasonable in most situations.
This allows the numeric program execution tocontinue undisturbed. Programs can mask individual exception types to indicatethat the x87 FPU should generate this safe, reasonable result whenever theexception occurs. The default exception fix-up activity is treated by the x87 FPUas part of the instruction causing the exception; no external indication of theexception is given (except that the instruction takes longer to execute when ithandles a masked exception.) When masked exceptions are detected, a flag isset in the numeric status register, but no information is preserved regardingwhere or when it was set.2.
A software exception handler can be invoked to handle the exception. When anumeric exception is unmasked and the exception occurs, the x87 FPU stopsfurther execution of the numeric instruction and causes a branch to a softwareexception handler. The exception handler can then implement any sort ofrecovery procedures desired for any numeric exception detectable by the x87FPU.D.3.2.1Automatic Exception Handling: Using Masked ExceptionsEach of the six exception conditions described above has a corresponding flag bit inthe x87 FPU status word and a mask bit in the x87 FPU control word.
If an exceptionD-12 Vol. 1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSis masked (the corresponding mask bit in the control word = 1), the processor takesan appropriate default action and continues with the computation.The processor has a default fix-up activity for every possible exception condition itmay encounter.
These masked-exception responses are designed to be safe and aregenerally acceptable for most numeric applications.For example, if the Inexact result (Precision) exception is masked, the system canspecify whether the x87 FPU should handle a result that cannot be representedexactly by one of four modes of rounding: rounding it normally, chopping it towardzero, always rounding it up, or always down. If the Underflow exception is masked,the x87 FPU will store a number that is too small to be represented in normalizedform as a denormal (or zero if it’s smaller than the smallest denormal).
Note thatwhen exceptions are masked, the x87 FPU may detect multiple exceptions in a singleinstruction, because it continues executing the instruction after performing itsmasked response. For example, the x87 FPU could detect a denormalized operand,perform its masked response to this exception, and then detect an underflow.As an example of how even severe exceptions can be handled safely and automatically using the default exception responses, consider a calculation of the parallelresistance of several values using only the standard formula (see Figure D-4). If R1becomes zero, the circuit resistance becomes zero.
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