Volume 1 Basic Architecture (794100), страница 83
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A complete specification of these cases, which applies to boththe Pentium and the Intel486 processors, is given in Section 5.1.21 in the PentiumProcessor Family Developer’s Manual: Volume 1.If NE = 0 but the IGNNE# input is active while an unmasked x87 FPU exception is ineffect, the processor disregards the exception, does not assert FERR#, andcontinues. If IGNNE# is then de-asserted and the x87 FPU exception has not beencleared, the processor will respond as described above.
(That is, an immediateexception case will assert FERR# immediately. A deferred exception case will assertFERR# and freeze just before the next x87 FPU or WAIT instruction.) The assertion ofIGNNE# is intended for use only inside the x87 FPU exception handler, where it isneeded if one wants to execute non-control x87 FPU instructions for diagnosis,before clearing the exception condition. When IGNNE# is asserted inside the exception handler, a preceding x87 FPU exception has already caused FERR# to beasserted, and the external interrupt hardware has responded, but IGNNE# assertionstill prevents the freeze at x87 FPU instructions. Note that if IGNNE# is left activeoutside of the x87 FPU exception handler, additional x87 FPU instructions may beexecuted after a given instruction has caused an x87 FPU exception.
In this case, ifthe x87 FPU exception handler ever did get invoked, it could not determine whichinstruction caused the exception.To properly manage the interface between the processor’s FERR# output, its IGNNE#input, and the IRQ13 input of the PIC, additional external hardware is needed. Arecommended configuration is described in the following section.D.2.1.2Recommended External Hardware to Support the MS-DOSCompatibility Sub-modeFigure D-1 provides an external circuit that will assure proper handling of FERR# andIGNNE# when an x87 FPU exception occurs.
In particular, it assures that IGNNE# willbe active only inside the x87 FPU exception handler without depending on the orderof actions by the exception handler. Some hardware implementations have been lessrobust because they have depended on the exception handler to clear the x87 FPUexception interrupt request to the PIC (FP_IRQ signal) before the handler causesFERR# to be de-asserted by clearing the exception from the x87 FPU itself.Figure D-2 shows the details of how IGNNE# will behave when the circuit inFigure D-1 is implemented. The temporal regions within the x87 FPU exceptionhandler activity are described as follows:1. The FERR# signal is activated by an x87 FPU exception and sends an interruptrequest through the PIC to the processor’s INTR pin.Vol.
1 D-5GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS2. During the x87 FPU interrupt service routine (exception handler) the processorwill need to clear the interrupt request latch (Flip Flop #1). It may also want toexecute non-control x87 FPU instructions before the exception is cleared from thex87 FPU. For this purpose the IGNNE# must be driven low. Typically in the PCenvironment an I/O access to Port 0F0H clears the external x87 FPU exceptioninterrupt request (FP_IRQ).
In the recommended circuit, this access also is usedto activate IGNNE#. With IGNNE# active, the x87 FPU exception handler mayexecute any x87 FPU instruction without being blocked by an active x87 FPUexception.3. Clearing the exception within the x87 FPU will cause the FERR# signal to bedeactivated and then there is no further need for IGNNE# to be active. In therecommended circuit, the deactivation of FERR# is used to deactivate IGNNE#.
Ifanother circuit is used, the software and circuit together must assure thatIGNNE# is deactivated no later than the exit from the x87 FPU exception handler.D-6 Vol. 1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS5(6(7,23RUW)+$GGUHVV'HFRGH9)))(55,QWHO3URFHVVRU3HQWLXP3URFHVVRU3HQWLXP3UR3URFHVVRU3599&/5))359,*11(,175,QWHUUXSW&RQWUROOHU)3B,54/(*(1'))Q)OLS)ORSQ&/5&OHDURU5HVHWFigure D-1. Recommended Circuit for MS-DOS Compatibility x87 FPUException HandlingIn the circuit in Figure D-1, when the x87 FPU exception handler accesses I/O port0F0H it clears the IRQ13 interrupt request output from Flip Flop #1 and also clocksout the IGNNE# signal (active) from Flip Flop #2. So the handler can activateIGNNE#, if needed, by doing this 0F0H access before clearing the x87 FPU exceptioncondition (which de-asserts FERR#).However, the circuit does not depend on the order of actions by the x87 FPU exception handler to guarantee the correct hardware state upon exit from the handler.
FlipFlop #2, which drives IGNNE# to the processor, has its CLEAR input attached to theinverted FERR#. This ensures that IGNNE# can never be active when FERR# is inac-Vol. 1 D-7GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERStive. So if the handler clears the x87 FPU exception condition before the 0F0Haccess, IGNNE# does not get activated and left on after exit from the handler.0F0H AddressDecodeFigure D-2.
Behavior of Signals During x87 FPU Exception HandlingD.2.1.3No-Wait x87 FPU Instructions Can Get x87 FPU Interrupt inWindowThe Pentium and Intel486 processors implement the “no-wait” floating-point instructions (FNINIT, FNCLEX, FNSTENV, FNSAVE, FNSTSW, FNSTCW, FNENI, FNDISI orFNSETPM) in the MS-DOS compatibility mode in the following manner. (See Section8.3.11, “x87 FPU Control Instructions,” and Section 8.3.12, “Waiting vs.
Non-waitingInstructions,” for a discussion of the no-wait instructions.)If an unmasked numeric exception is pending from a preceding x87 FPU instruction,a member of the no-wait class of instructions will, at the beginning of its execution,assert the FERR# pin in response to that exception just like other x87 FPU instructions, but then, unlike the other x87 FPU instructions, FERR# will be de-asserted.This de-assertion was implemented to allow the no-wait class of instructions toproceed without an interrupt due to any pending numeric exception.
However, thebrief assertion of FERR# is sufficient to latch the x87 FPU exception request into mosthardware interface implementations (including Intel’s recommended circuit).All the x87 FPU instructions are implemented such that during their execution, thereis a window in which the processor will sample and accept external interrupts. Ifthere is a pending interrupt, the processor services the interrupt first beforeresuming the execution of the instruction. Consequently, it is possible that the nowait floating-point instruction may accept the external interrupt caused by it’s ownassertion of the FERR# pin in the event of a pending unmasked numeric exception,D-8 Vol.
1GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSwhich is not an explicitly documented behavior of a no-wait instruction. This processis illustrated in Figure D-3.Exception GeneratingFloating-PointInstructionAssertion of FERR#by the ProcessorStart of the “No-Wait”Floating-PointInstructionSystemDependentDelayCase 1External InterruptSampling WindowAssertion of INTR Pinby the SystemCase 2Window ClosedFigure D-3.
Timing of Receipt of External InterruptFigure D-3 assumes that a floating-point instruction that generates a “deferred”error (as defined in the Section D.2.1.1, “Basic Rules: When FERR# Is Generated”),which asserts the FERR# pin only on encountering the next floating-point instruction,causes an unmasked numeric exception. Assume that the next floating-point instruction following this instruction is one of the no-wait floating-point instructions.
TheFERR# pin is asserted by the processor to indicate the pending exception on encountering the no-wait floating-point instruction. After the assertion of the FERR# pin theno-wait floating-point instruction opens a window where the pending external interrupts are sampled.Then there are two cases possible depending on the timing of the receipt of the interrupt via the INTR pin (asserted by the system in response to the FERR# pin) by theprocessor.Case 1If the system responds to the assertion of FERR# pin by the no-waitfloating-point instruction via the INTR pin during this window thenthe interrupt is serviced first, before resuming the execution of theno-wait floating-point instruction.Case 2If the system responds via the INTR pin after the window has closedthen the interrupt is recognized only at the next instruction boundary.Vol. 1 D-9GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERSThere are two other ways, in addition to Case 1 above, in which a no-wait floatingpoint instruction can service a numeric exception inside its interrupt window.
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