Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 42
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Values in memory can be in single-precision ordouble-precision floating-point, word integer, or short integer format.If one operand is specified, the instruction subtracts the value in ST(0) from the value in memory andstores the result in ST(0).If two operands are specified, it subtracts the value in ST(0) from the value in another floating-pointregister or vice versa.The FSUBRP instruction pops the x87 register stack after performing the subtraction.The no-operand version of the instruction always pops the register stack. In some assemblers, themnemonic for this instruction is FSUBR rather than FSUBRP.The FISUBR instruction converts a signed integer operand to double-extended-precision formatbefore performing the subtraction.The FSUBR instructions perform the reverse operations of the FSUB instructions.MnemonicOpcodeDescriptionFSUBR ST(0),ST(i)D8 E8+iReplace ST(0) with ST(i) - ST(0).FSUBR ST(i),ST(0)DC E0+iReplace ST(i) with ST(0) - ST(i).FSUBR mem32realD8 /5Replace ST(0) with mem32real - ST(0).FSUBR mem64realDC /5Replace ST(0) with mem64real - ST(0).FSUBRPDE E1Replace ST(1) with ST(0) - ST(1) and pop x87 stack.FSUBRP ST(i),ST(0)DE E0+iReplace ST(i) with ST(0) - ST(i) and pop x87 stack.FISUBR mem16intDE /5Replace ST(0) with mem16int - ST(0).FISUBR mem32intDA /5Replace ST(0) with mem32int - ST(0).Related InstructionsFSUB, FSUBP, FISUBrFLAGS AffectedNoneInstruction ReferenceFSUBRx313AMD64 Technology26569—Rev.
3.08—July 2007x87 Condition Codex87 Condition CodeValueC0UC1Description0x87 stack underflow, if an x87 register stack fault was detected.0Result was rounded down, if a precision exception was detected.1Result was rounded up, if a precision exception was detected.C2UC3UNote: A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) is set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or wasnon-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXAn unmasked x87 floating-point exception was pending.x87 floating-pointexception pending,#MFXx87 Floating-Point Exception Generated, #MFXXXA source operand was an SNaN value or an unsupportedformat.XXX+infinity was subtracted from +infinity.XXX–infinity was subtracted from –infinity.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.Overflow exception(OE)XXXA rounded result was too large to fit into the format of thedestination operand.Invalid-operationexception (IE)314FSUBRxInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyVirtual8086 ProtectedExceptionRealUnderflow exception(UE)XXXA rounded result was too small to fit into the format of thedestination operand.Precision exception(PE)XXXA result could not be represented exactly in the destinationformat.Instruction ReferenceCause of ExceptionFSUBRx315AMD64 Technology26569—Rev. 3.08—July 2007FTSTFloating-Point Test with ZeroCompares the value in ST(0) with 0.0, and sets the condition code flags in the x87 status word asshown in the x87 Condition Code table below. The instruction ignores the sign distinction between–0.0 and +0.0.MnemonicOpcodeFTSTDescriptionD9 E4Compare ST(0) to 0.0.Related InstructionsFCOM, FCOMP, FCOMPP, FCOMI, FCOMIP, FICOM, FICOMP, FUCOMI, FUCOMIP, FUCOM,FUCOMP, FUCOMPP, FXAMrFLAGS AffectedNonex87 Condition CodeC3C2C1C0Compare Result0000ST(0) > 0.00001ST(0) < 0.01000ST(0) = 0.01101ST(0) was unorderedExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE)XXXA source operand was a SNaN value, a QNaN value, or anunsupported format.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.316FTSTInstruction Reference26569—Rev.
3.08—July 2007FUCOMFUCOMPFUCOMPPAMD64 TechnologyFloating-Point Unordered CompareCompares the value in ST(0) to the value in another x87 register, and sets the condition codes in thex87 status word as shown in the x87 Condition Code table below.If no source operand is specified, the instruction compares the value in ST(0) to that in ST(1).After making the comparison, the FUCOMP instruction pops the x87 stack register and theFUCOMPP instruction pops the x87 stack register twice.The instruction carries out the same comparison operation as the FCOM instructions, but sets theinvalid-operation exception (IE) bit in the x87 status word to 1 when either or both operands are anSNaN or are in an unsupported format.
If either or both operands is a QNaN, it sets the condition codeflags to unordered, but does not set the IE bit. The FCOM instructions, on the other hand, raise an IEexception when either or both of the operands are a NaN value or are in an unsupported format.Support for the FUCOM(P(P)) instruction is indicated by EDX bit 0 (FPU) and EDX bit 15 (CMOV)as returned by either CPUID function 0000_0001h or CPUID function 8000_0001h.MnemonicOpcodeDescriptionFUCOMDD E1Compare ST(0) to ST(1) and set condition code flags toreflect the results of the comparison.FUCOM ST(i)DD E0+iCompare ST(0) to ST(i) and set condition code flags toreflect the results of the comparison.FUCOMPDD E9Compare ST(0) to ST(1), set condition code flags to reflectthe results of the comparison, and pop the x87 registerstack.FUCOMP ST(i)DD E8+iCompare ST(0) to ST(i), set condition code flags to reflectthe results of the comparison, and pop the x87 registerstack.FUCOMPPDA E9Compare ST(0) to ST(1), set condition code flags to reflectthe results of the comparison, and pop the x87 register stacktwice.Related InstructionsFCOM, FCOMPP, FCOMI, FCOMIP, FICOM, FICOMP, FTST, FUCOMI, FUCOMIP, FXAMrFLAGS AffectedNoneInstruction ReferenceFUCOMx317AMD64 Technology26569—Rev.
3.08—July 2007x87 Condition CodeC3C2C1C0Compare Result0000ST(0) > source0001ST(0) < source1000ST(0) = source1101Operands were unorderedExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE)XXXA source operand was an SNaN value or an unsupportedformat.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.318FUCOMxInstruction Reference26569—Rev.
3.08—July 2007FUCOMIFUCOMIPAMD64 TechnologyFloating-Point Unordered Compare and SeteFLAGSCompares the contents of ST(0) with the contents of another floating-point register, and sets the zeroflag (ZF), parity flag (PF), and carry flag (CF) as shown in the rFLAGS Affected table below.Unlike FCOMI and FCOMIP, the FUCOMI and FUCOMIP instructions do not set the invalidoperation exception (IE) bit in the x87 status word for QNaNs.After completing the comparison, FUCOMIP pops the x87 register stack.Support for the FUCOMI(P) instruction is indicated by EDX bit 0 (FPU) and EDX bit 15 (CMOV) asreturned by either CPUID function 0000_0001h or CPUID function 8000_0001h.MnemonicOpcodeDescriptionFUCOMI ST(0),ST(i)DB E8+iCompare ST(0) to ST(i) and set eFLAGS to reflect the resultof the comparison.FUCOMIP ST(0),ST(i)DF E8+iCompare ST(0) to ST(i), set eFLAGS to reflect the result ofthe comparison, and pop the x87 register stack.Related InstructionsFCOM, FCOMPP, FCOMI, FCOMIP, FICOM, FICOMP, FTST, FUCOM, FUCOMP, FUCOMPP,FXAMrFLAGS AffectedZFPFCFCompare Result000ST(0) > source001ST(0) < source100ST(0) = source111Operands were unorderedx87 Condition Codex87 Condition CodeValueDescriptionC0C10C2C3Note: A flag set to 1 or cleared to 0 is M (modified).
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