Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 43
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Unaffected flags are blank. Undefined flags are U.Instruction ReferenceFUCOMIx319AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionInvalid opcode, #UDXXXThe conditional move instructions are not supported, asindicated by EDX bit 0 and EDX bit 15 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) is set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE)XXXA source operand was an SNaN value or an unsupportedformat.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.320FUCOMIxInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyFWAIT(WAIT)Wait for Unmasked x87 Floating-PointExceptionsForces the processor to test for pending unmasked floating-point exceptions before proceeding.If there is a pending floating-point exception and CR0.NE = 1, a numeric exception (#MF) isgenerated. If there is a pending floating-point exception and CR0.NE = 0, FWAIT asserts the FERRoutput signal, then waits for an external interrupt.This instruction is useful for insuring that unmasked floating-point exceptions are handled beforealtering the results of a floating point instruction.FWAIT and WAIT are synonyms for the same opcode.MnemonicOpcodeFWAITDescription9BCheck for any pending floating-point exceptions.Related InstructionsNonerFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueC0UC1UC2UC3UDescriptionNote: A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealDevice not available,#NMXXXThe monitor coprocessor bit (MP) and the task switch bit(TS) of the control register (CR0) were both set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.Instruction ReferenceCause of ExceptionFWAIT (WAIT)321AMD64 Technology26569—Rev. 3.08—July 2007FXAMFloating-Point ExamineExamines the value in ST(0) and sets the C0, C2, and C3 condition code flags in the x87 status word asshown in the x87 Condition Code table below to indicate whether the value is a NaN, infinity, zero,empty, denormal, normal finite, or unsupported value.
The instruction also sets the C1 flag to indicatethe sign of the value in ST(0) (0 = positive, 1 = negative).MnemonicFXAMOpcodeD9 E5DescriptionCharacterize the number in the ST(0) register.Related InstructionsFCOM, FCOMP, FCOMPP, FCOMI, FCOMIP, FICOM, FICOMP, FTST, FUCOM, FUCOMI,FUCOMIP, FUCOMP, FUCOMPPrFLAGS AffectedNonex87 Condition Code322C3C2C1C00000+unsupportedformat0001+NaN0010–unsupportedformat0011–NaN0100+normal0101+infinity0110–normal0111–infinity1000+01001+empty1010–01011–empty1100+denormal1110–denormalFXAMMeaningInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) is set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.Instruction ReferenceFXAM323AMD64 Technology26569—Rev. 3.08—July 2007FXCHFloating-Point ExchangeExchanges the value in ST(0) with the value in any other x87 register. If no operand is specified, theinstruction exchanges the values in ST(0) and ST(1).Use this instruction to move a value from an x87 register to ST(0) for subsequent processing by afloating-point instruction that can only operate on ST(0).MnemonicOpcodeDescriptionFXCHD9 C9Exchange the contents of ST(0) and ST(1).FXCH ST(i)D9 C8+iExchange the contents of ST(0) and ST(i).Related InstructionsFLD, FST, FSTPrFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueC0UC10C2UC3UDescriptionNote: A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of the controlregister (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE) withstack fault (SF)324XXXAn x87 stack underflow occurred.FXCHInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyFXRSTORRestore XMM, MMX™, and x87 StateRestores the XMM, MMX, and x87 state. The data loaded from memory is the state informationpreviously saved using the FXSAVE instruction. Restoring data with FXRSTOR that had beenpreviously saved with an FSAVE (rather than FXSAVE) instruction results in an incorrect restoration.If FXRSTOR results in set exception flags in the loaded x87 status word register, and these exceptionsare unmasked in the x87 control word register, a floating-point exception occurs when the nextfloating-point instruction is executed (except for the no-wait floating-point instructions).If the restored MXCSR register contains a set bit in an exception status flag, and the correspondingexception mask bit is cleared (indicating an unmasked exception), loading the MXCSR register frommemory does not cause a SIMD floating-point exception (#XF).FXRSTOR does not restore the x87 error pointers (last instruction pointer, last data pointer, and lastopcode), except in the relatively rare cases in which the exception-summary (ES) bit in the x87 statusword is set to 1, indicating that an unmasked x87 exception has occurred.The architecture supports two 512-bit memory formats for FXRSTOR, a 64-bit format that loadsXMM0-XMM15, and a 32-bit legacy format that loads only XMM0-XMM7.
If FXRSTOR is executedin 64-bit mode, the 64-bit format is used, otherwise the 32-bit format is used. When the 64-bit format isused, if the operand-size is 64-bit, FXRSTOR loads the x87 pointer registers as offset64, otherwise itloads them as sel:offset32. For details about the memory format used by FXRSTOR, see "SavingMedia and x87 Processor State" in Volume 2.If the fast-FXSAVE/FXRSTOR (FFXSR) feature is enabled in EFER, FXRSTOR does not restore theXMM registers (XMM0-XMM15) when executed in 64-bit mode at CPL 0. MXCSR is restoredwhether fast-FXSAVE/FXRSTOR is enabled or not. Software can use CPUID to determine whetherthe fast-FXSAVE/FXRSTOR feature is available.
(See “CPUID” in Volume 3.)If the operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0, the savedimage of XMM0–XMM15 and MXCSR is not loaded into the processor. A general-protectionexception occurs if the FXRSTOR instruction attempts to load non-zero values into reserved MXCSRbits. Software can use MXCSR_MASK to determine which bits of MXCSR are reserved. For detailson the MXCSR_MASK, see “128-Bit, 64-Bit, and x87 Programming” in Volume 2..MnemonicFXRSTOR mem512envOpcode0F AE /1DescriptionRestores XMM, MMX™, and x87 state from 512-bytememory location.Related InstructionsFWAIT, FXSAVEInstruction ReferenceFXRSTOR325AMD64 Technology26569—Rev.
3.08—July 2007rFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCMMM171514PMUMOMZMDMIMDAZPEUEOEZEDEIEMMMMMMMMMMMMMM131211109876543210Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank. Shaded fields are reserved.ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe FXSAVE/FXRSTOR instructions are notsupported, as indicated by bit 24 of CPUID function0000_0001h or function 8000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit,or was non-canonical.XXXA memory address exceeded the data segment limitor was non-canonical.XA null data segment was used to reference memory.Invalid opcode, #UDGeneral protection, #GPPage fault, #PF326XXXThe memory operand was not aligned on a 16-byteboundary.XXXOnes were written to the reserved bits in MXCSR.XXA page fault resulted from the execution of theinstruction.FXRSTORInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyFXSAVESave XMM, MMX™, and x87 StateSaves the XMM, MMX, and x87 state. A memory location that is not aligned on a 16-byte boundarycauses a general-protection exception.Unlike FSAVE and FNSAVE, FXSAVE does not alter the x87 tag bits. The contents of the savedMMX/x87 data registers are retained, thus indicating that the registers may be valid (or whatever othervalue the x87 tag bits indicated prior to the save).
To invalidate the contents of the MMX/x87 dataregisters after FXSAVE, software must execute an FINIT instruction. Also, FXSAVE (like FNSAVE)does not check for pending unmasked x87 floating-point exceptions. An FWAIT instruction can beused for this purpose.FXSAVE does not save the x87 pointer registers (last instruction pointer, last data pointer, and lastopcode), except in the relatively rare cases in which the exception-summary (ES) bit in the x87 statusword is set to 1, indicating that an unmasked x87 exception has occurred.The architecture supports two 512-bit memory formats for FXSAVE, a 64-bit format that savesXMM0-XMM15, and a 32-bit legacy format that saves only XMM0-XMM7.
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