Volume 1 Application Programming (794095), страница 63
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Unmasking the exception type causes the processor to branch to the #MFexception service routine when an exception occurs. For details about the processor’s responses tomasked and unmasked exceptions, see “x87 Floating-Point Exception Causes” on page 280.Precision Control (PC). Bits 9–8. Software can set this field to specify the precision of x87 floating-point calculations, as shown in Table 6-1. Details on each precision are given in “Data Types” onpage 250. The default precision is double-extended-precision. Precision control affects only theFADDx, FSUBx, FMULx, FDIVx, and FSQRT instructions.
For further details on precision, see“Precision” on page 261.Table 6-1.Precision Control (PC) SummaryPC Value(binary)Data Type00Single precision01reserved10Double precision11Double-extended precision (default)Rounding Control (RC). Bits 11–10. Software can set this field to specify how the results of x87instructions are to be rounded. Table 6-2 lists the four rounding modes, which are defined by the IEEE754 standard.Table 6-2.RC Value00(default)Types of RoundingModeType of RoundingThe rounded result is the representable value closest toRound to nearest the infinitely precise result. If equally close, the evenvalue (with least-significant bit 0) is taken.01Round downThe rounded result is closest to, but no greater than, theinfinitely precise result.10Round upThe rounded result is closest to, but no less than, theinfinitely precise result.11Round towardzeroThe rounded result is closest to, but no greater inabsolute value than, the infinitely precise result.x87 Floating-Point Programming245AMD64 Technology24592—Rev.
3.13—July 2007Round-to-nearest is the default rounding mode. It provides a statistically unbiased estimate of the trueresult, and is suitable for most applications. Rounding modes apply to all arithmetic operations exceptcomparison and remainder. They have no effect on operations that produce not-a-number (NaN)results. For further details on rounding, see “Rounding” on page 261.Infinity Bit (Y). Bit 12.
This bit is obsolete. It can be read and written, but the value has no meaning.On pre-386 processor implementations, the bit specified the affine (Y = 1) or projective (Y = 0)infinity. The AMD64 architecture uses only the affine infinity, which specifies distinct positive andnegative infinity values.6.2.4 x87 Tag Word Register (FTW)The x87 tag word register contains a 2-bit tag field for each x87 physical data register. These tag fieldscharacterize the register’s data. Figure 6-5 shows the format of the tag word.15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0TAG(FPR7)TAG(FPR6)TAG(FPR5)TAG(FPR4)TAG(FPR3)TAG(FPR2)TAG(FPR1)TAG(FPR0)Tag Values00 = Valid01 = Zero10 = Special11 = EmptyFigure 6-5.
x87 Tag Word Register (FTW)In the memory image saved by the instructions described in “x87 Environment” on page 248, each x87physical data register has two tag bits which are encoded according to the Tag Values shown inFigure 6-5. Internally, the hardware may maintain only a single bit that indicates whether theassociated register is empty or full. The mapping between such a 1-bit internal tag and the 2-bitsoftware-visible architectural representation saved in memory is shown in Table 6-3 on page 247. Insuch a mapping, whenever software saves the tag word, the processor expands the internal 1-bit tagstate to the 2-bit architectural representation by examining the contents of the x87 registers, asdescribed in “128-Bit, 64-Bit, and x87 Programming” in Volume 2.246x87 Floating-Point Programming24592—Rev.
3.13—July 2007Table 6-3.AMD64 TechnologyMapping Between Internal and Software-Visible Tag BitsArchitectural State (Software-Visible)StateHardware StateBit ValueValid00Zero01Special(NaN, infinity, denormal, or unsupported)10Empty11FullEmptyThe FINIT and FNINIT instructions write the tag word so that it specifies all floating-point registers asempty. Execution of 64-bit media instructions that write to an MMX™ register alter the tag bits bysetting all the registers to full, and thus they may affect execution of subsequent x87 floating-pointinstructions.
For details, see “Mixing Media Code with x87 Code” on page 233.6.2.5 Pointers and Opcode StateThe x87 instruction pointer, instruction opcode, and data pointer are part of the x87 environment (nondata processor state) that is loaded and stored by the instructions described in “x87 Environment” onpage 248. Figure 6-6 illustrates the pointer and opcode state.
Execution of all x87 instructions—exceptcontrol instructions (see “Control” on page 274)—causes the processor to store this state in hardware.For convenience, the pointer and opcode state is illustrated here as registers. However, the manner ofstoring this state in hardware depends on the hardware implementation. The AMD64 architecturespecifies only the software-visible state that is saved in memory. (See “Media and x87 Processor State”in Volume 2 for details of the memory images.)Instruction Pointer (rIP)Data Pointer63Opcode100513-138.epsFigure 6-6.x87 Pointers and Opcode StateLast x87 Instruction Pointer.
The contents of the 64-bit last-instruction pointer depends on theoperating mode, as follows:•64-Bit Mode—The pointer contains the 64-bit RIP offset of the last non-control x87 instructionexecuted (see “Control” on page 274 for a definition of control instructions). The 16-bit code-x87 Floating-Point Programming247AMD64 Technology••24592—Rev. 3.13—July 2007segment (CS) selector is not saved. (It is the operating system’s responsibility to ensure that the 64bit state-restoration is executed in the same code segment as the preceding 64-bit state-store.)Legacy Protected Mode and Compatibility Mode—The pointer contains the 16-bit code-segment(CS) selector and the 16-bit or 32-bit eIP of the last non-control x87 instruction executed.Legacy Real Mode and Virtual-8086 Mode—The pointer contains the 20-bit or 32-bit linearaddress (CS base + eIP) of the last non-control x87 instruction executed.The FINIT and FNINIT instructions clear all bits in this pointer.Last x87 Opcode.
The 11-bit instruction opcode holds a permutation of the two-byte instructionopcode from the last non-control x87 floating-point instruction executed by the processor. The opcodefield is formed as follows:••Opcode Field[10:8] = First x87-opcode byte[2:0].Opcode Field[7:0] = Second x87-opcode byte[7:0].For example, the x87 opcode D9 F8 (floating-point partial remainder) is stored as 001_1111_1000b.The low-order three bits of the first opcode byte, D9 (1101_1001b), are stored in bits 10–8. The secondopcode byte, F8 (1111_1000b), is stored in bits 7–0.
The high-order five bits of the first opcode byte(1101_1b) are not needed because they are identical for all x87 instructions.Last x87 Data Pointer. The operating mode determines the value of the 64-bit data pointer, asfollows:•••64-Bit Mode—The pointer contains the 64-bit offset of the last memory operand accessed by thelast non-control x87 instruction executed.Legacy Protected Mode and Compatibility Mode—The pointer contains the 16-bit data-segmentselector and the 16-bit or 32-bit offset of the last memory operand accessed by an executed noncontrol x87 instruction.Legacy Real Mode and Virtual-8086 Mode—The pointer contains the 20-bit or 32-bit linearaddress (segment base + offset) of the last memory operand accessed by an executed non-controlx87 instruction.The FINIT and FNINIT instructions clear all bits in this pointer.6.2.6 x87 EnvironmentThe x87 environment—or non-data processor state—includes the following processor state:••••••x87 control word register (FCW)x87 status word register (FSW)x87 tag word (FTW)last x87 instruction pointerlast x87 data pointerlast x87 opcode248x87 Floating-Point Programming24592—Rev.
3.13—July 2007AMD64 TechnologyTable 6-4 lists the x87 instructions can access this x87 processor state.Table 6-4.Instructions that Access the x87 EnvironmentInstructionDescriptionState AccessedFINITFloating-Point InitializeEntire EnvironmentFNINITFloating-Point No-Wait InitializeEntire EnvironmentFNSAVEFloating-Point No-Wait Save StateEntire EnvironmentFRSTORFloating-Point Restore StateEntire EnvironmentFSAVEFloating-Point Save StateEntire EnvironmentFLDCWFloating-Point Load x87 Control Wordx87 Control WordFNSTCWFloating-Point No-Wait Store ControlWordx87 Control WordFSTCWFloating-Point Store Control Wordx87 Control WordFNSTSWFloating-Point No-Wait Store StatusWordx87 Status WordFSTSWFloating-Point Store Status Wordx87 Status WordFLDENVFloating-Point Load x87 EnvironmentEnvironment, NotIncluding x87 DataRegistersFNSTENVFloating-Point No-Wait StoreEnvironmentEnvironment, NotIncluding x87 DataRegistersFSTENVFloating-Point Store EnvironmentEnvironment, NotIncluding x87 DataRegistersFor details on how the x87 environment is stored in memory, see “Media and x87 Processor State” inVolume 2.6.2.7 Floating-Point Emulation (CR0.EM)The operating system can set the floating-point software-emulation (EM) bit in control register 0(CR0) to 1 to allow software emulation of x87 instructions.
If the operating system has setCR0.EM = 1, the processor does not execute x87 instructions. Instead, a device-not-availableexception (#NM) occurs whenever an attempt is made to execute such an instruction, except thatsetting CR0.EM to 1 does not cause an #NM exception when the WAIT or FWAIT instruction isexecuted. For details, see “System-Control Registers” in Volume 2.x87 Floating-Point Programming249AMD64 Technology6.324592—Rev. 3.13—July 2007Operands6.3.1 Operand AddressingOperands for x87 instructions are referenced by the opcodes.
Operands can be located either in x87registers or memory. Immediate operands are not used in x87 floating-point instructions, and I/O portscannot be directly addressed by x87 floating-point instructions.Memory Operands. Most x87 floating-point instructions can take source operands from memory,and a few of the instructions can write results to memory. The following sections describe the methodsand conditions for addressing memory operands:••“Memory Addressing” on page 14 describes the general methods and conditions for addressingmemory operands.“Instruction Prefixes” on page 278 describes the use of address-size instruction overrides by 64-bitmedia instructions.Register Operands.
Most x87 floating-point instructions can read source operands from and writeresults to x87 registers. Most instructions access the ST(0)–ST(7) register stack. For a few instructions,the register types also include the x87 control word register, the x87 status word register, and (forFSTSW and FNSTSW) the AX general-purpose register.6.3.2 Data TypesFigure 6-7 on page 251 shows register images of the x87 data types. These include three scalarfloating-point formats (80-bit double-extended-precision, 64-bit double-precision, and 32-bit singleprecision), three scalar signed-integer formats (quadword, doubleword, and word), and an 80-bitpacked binary-coded decimal (BCD) format.
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