Volume 1 Application Programming (794095), страница 66
Текст из файла (страница 66)
1111000 ... 001 1.000 ... 000toto111 ... 110 1.111 ... 111Negative Infinity (-∞) 1111 ... 111 1.000 ... 000SNaN11.000 ... 001111 ... 111 to1.011 ... 111QNaN411.100 ... 000111 ... 111 to1.111 ... 111NegativeNegative PseudoFloating-PointDenormal3NumbersNegative NormalNegativeNon-NumbersNote:1. The actual exponent field length is 8, 11, or 15 bits, depending on operand precision.2. The “1.” and “0.” prefixes represent the implicit or explicit integer bit. The actual fraction field length is 23, 52, or 63 bits, depending on operand precision.3. Pseudo-denormals can only occur in double-extended-precision format, becausethey require an explicit integer bit.4.
The floating-point indefinite value is a QNaN with a negative sign and a significandwhose value is 1.100 ... 000.Unsupported Encodings. Table 6-9 on page 260 shows the encodings of unsupported values. Thesevalues can exist only in the double-extended-precision format, because they require an explicit integerbit. The processor does not generate them as results, and they cause an invalid-operation exception (IE)when used as source operands.Indefinite Values. Floating-point, integer, and packed-decimal data types each have a uniqueencoding that represents an indefinite value.
The processor returns an indefinite value when a maskedinvalid-operation exception (IE) occurs. The indefinite values for various data types are provided inTable 4-7 on page 132.For example, if a floating-point arithmetic operation is attempted using a source operand which is in anunsupported format, and IE exceptions are masked, the floating-point indefinite value is returned asthe result. Or, if an integer store instruction overflows its destination data type, and IE exceptions aremasked, the integer indefinite value is returned as the result.x87 Floating-Point Programming259AMD64 TechnologyTable 6-9.24592—Rev. 3.13—July 2007Unsupported Floating-Point EncodingsClassificationSignBiasedExponent1Significand2Positive Pseudo-NaN0111 ...
1110.111 ... 111to0.000 ... 001Positive Pseudo-Infinity0111 ... 1110.000 ... 000Positive Unnormal0111 ... 110to000 ... 0010.111 ... 111to0.000 ... 000Negative Unnormal1000 ... 001to111 ... 1100.000 ... 000to0.111 ... 111Negative Pseudo-Infinity1111 ... 1110.000 ... 000Negative Pseudo-NaN1111 ... 1110.000 ... 001to0.111 ... 111Note:1. The actual exponent field length is 15 bits.2. The “0.” prefix represent the explicit integer bit. The actual fraction field length is 63bits.Table 6-10 shows the encodings of the indefinite values for each data type.
For floating-point numbers,the indefinite value is a special form of QNaN. For integers, the indefinite value is the largestrepresentable negative two’s-complement number, 80...00h. (This value is interpreted as the largestrepresentable negative number, except when a masked IE exception occurs, in which case it isinterpreted as an indefinite value.) For packed-decimal numbers, the indefinite value has no othermeaning than indefinite.Table 6-10. Indefinite-Value EncodingsData TypeIndefinite EncodingSingle-Precision Floating-PointFFC0_0000hDouble-Precision Floating-PointFFF8_0000_0000_0000hExtended-Precision Floating-PointFFFF_C000_0000_0000_0000h16-Bit Integer8000h32-Bit Integer8000_0000h64-Bit Integer8000_0000_0000_0000h80-bit BCDFFFF_C000_0000_0000_0000h260x87 Floating-Point Programming24592—Rev.
3.13—July 2007AMD64 Technology6.3.5 PrecisionThe Precision control (PC) field comprises bits 9–8 of the x87 control word (“x87 Control WordRegister (FCW)” on page 244). This field specifies the precision of floating-point calculations for theFADDx, FSUBx, FMULx, FDIVx, and FSQRT instructions, as shown in Table 6-11.Table 6-11. Precision Control Field (PC) Values and Bit PrecisionPC FieldData TypePrecision (bits)24100Single precision01reserved10Double precision53111Double-extended precision64Note:1. The single-precision and double-precision bit counts include the implied integer bit.The default precision is double-extended-precision. Selecting double-precision or single-precisionreduces the size of the significand to 53 bits or 24 bits, but keeps the exponent in double extendedrange.
The reduced precision is provided to support the IEEE 754 standard. When using reducedprecision, rounding clears the unused bits on the right of the significand to 0s.6.3.6 RoundingThe rounding control (RC) field comprises bits 11–10 of the x87 control word (“x87 Control WordRegister (FCW)” on page 244). This field specifies how the results of x87 floating-point computationsare rounded. Rounding modes apply to most arithmetic operations but not to comparison or remainder.They have no effect on operations that produce NaN results.The IEEE 754 standard defines the four rounding modes as shown in Table 6-12.Table 6-12.
Types of RoundingRC Value00(default)ModeType of RoundingThe rounded result is the representable valueclosest to the infinitely precise result. If equallyRound to nearestclose, the even value (with least-significant bit 0)is taken.01Round downThe rounded result is closest to, but no greaterthan, the infinitely precise result.10Round upThe rounded result is closest to, but no less than,the infinitely precise result.11Round towardzeroThe rounded result is closest to, but no greater inabsolute value than, the infinitely precise result.Round to nearest is the default (reset) rounding mode. It provides a statistically unbiased estimate ofthe true result, and is suitable for most applications.
The other rounding modes are directed roundings:x87 Floating-Point Programming261AMD64 Technology24592—Rev. 3.13—July 2007round up (toward +∞), round down (toward –∞), and round toward zero. Round up and round down areused in interval arithmetic, in which upper and lower bounds bracket the true result of a computation.Round toward zero takes the smaller in magnitude, that is, always truncates.The processor produces a floating-point result defined by the IEEE standard to be infinitely precise.This result may not be representable exactly in the destination format, because only a subset of thecontinuum of real numbers finds exact representation in any particular floating-point format.Rounding modifies such a result to conform to the destination format, thereby making the resultinexact and also generating a precision exception (PE), as described in “x87 Floating-Point ExceptionCauses” on page 280.Suppose, for example, the following 24-bit result is to be represented in single-precision format, where“E2 1010” represents the biased exponent:1.0011 0101 0000 0001 0010 0111 E2 1010This result has no exact representation, because the least-significant 1 does not fit into the singleprecision format, which allows for only 23 bits of fraction.
The rounding control field determines thedirection of rounding. Rounding introduces an error in a result that is less than one unit in the last place(ulp), that is, the least-significant bit position of the floating-point representation.6.4Instruction SummaryThis section summarizes the functions of the x87 floating-point instructions. The instructions areorganized here by functional group—such as data-transfer, arithmetic, and so on. More detail onindividual instructions is given in the alphabetically organized “x87 Floating-Point InstructionReference” in Volume 5.Software running at any privilege level can use any of these instructions, if the CPUID instructionreports support for the instructions (see “Feature Detection” on page 279). Most x87 instructions takefloating-point data types for both their source and destination operands, although some x87 dataconversion instructions take integer formats for their source or destination operands.6.4.1 SyntaxEach instruction has a mnemonic syntax used by assemblers to specify the operation and the operandsto be used for source and destination (result) data.
Many of x87 instructions have the following syntax:MNEMONIC st(j), st(i)Figure 6-10 on page 263 shows an example of the mnemonic syntax for a floating-point add (FADD)instruction.262x87 Floating-Point Programming24592—Rev. 3.13—July 2007AMD64 TechnologyFADD st(0), st(i)MnemonicFirst Source Operandand Destination OperandSecond Source OperandFigure 6-10.513-146.epsMnemonic Syntax for Typical InstructionThis example shows the FADD mnemonic followed by two operands, both of which are 80-bit stackregister operands. Most instructions take source operands from an x87 stack register and/or memoryand write their results to a stack register or memory. Only two of the instructions (FSTSW andFNSTSW) can access a general-purpose registers (GPR), and none access the 128-bit media (XMM)registers. Although the MMX registers map to the x87 registers, the contents of the MMX registerscannot be accessed meaningfully using x87 instructions.Instructions can have one or more prefixes that modify default operand properties.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
