Volume 1 Application Programming (794095), страница 62
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For example, FADDP (floating-point add and pop) behaves exactly likeFADD (floating-point add), except that it pops the stack after completion. Programs that use the x87registers as a flat register file rather than as a stack would use non-popping versions of instructions toensure that the TOP remains unchanged.
However, loads (pushes) without corresponding pops cancause the stack to overflow, which occurs when a value is pushed or loaded into an x87 register that is240x87 Floating-Point Programming24592—Rev. 3.13—July 2007AMD64 Technologynot empty (as indicated by the register’s tag bits). To prevent overflow, the FXCH (floating-pointexchange) instruction can be used to access stack registers, giving the appearance of a flat register file,but all x87 programs must be aware of the register file’s stack organization.The FINCSTP and FDECSTP instructions can be used to increment and decrement, respectively, theTOP, modulo-8, allowing the stack top to wrap around to the bottom of the eight-register file whenincremented beyond the top of the file, or to wrap around to the top of the register file whendecremented beyond the bottom of the file.
Neither the x87 tag word nor the contents of the floatingpoint stack itself is updated when these instructions are used.6.2.2 x87 Status Word Register (FSW)The 16-bit x87 status word register contains information about the state of the floating-point unit,including the top-of-stack pointer (TOP), four condition-code bits, exception-summary flag, stackfault flag, and six x87 floating-point exception flags. Figure 6-3 on page 242 shows the format of thisregister. All bits can be read and written, however values written to the B and ES bits (bits 15 and 7) areignored.The FRSTOR and FXRSTOR instructions load the status word from memory.
The FSTSW, FNSTSW,FSAVE, FNSAVE, FXSAVE, FSTENV, and FNSTENV instructions store the status word to memory.The FCLEX and FNCLEX instructions clear the exception flags. The FINIT and FNINIT instructionsclear all bits in the status-word.x87 Floating-Point Programming241AMD64 Technology24592—Rev. 3.13—July 200715 14 13 12 11 10 9C3BTOP765C C C E2 1 0 SSFP U O Z D IE E E E E EBitsMnemonic1514BC3TOP13–111098765C2C1C0ESSF1PEUEOEZEDE0IE432843210Descriptionx87 Floating-Point Unit BusyCondition CodeTop of Stack Pointer000 = FPR0111 = FPR7Condition CodeCondition CodeCondition CodeException StatusStack FaultException FlagsPrecision ExceptionUnderflow ExceptionOverflow ExceptionZero-Divide ExceptionDenormalized-OperandExceptionInvalid-Operation ExceptionFigure 6-3.
x87 Status Word Register (FSW)The bits in the x87 status word are defined immediately below, starting with bit 0. The six exceptionflags (IE, DE, ZE, OE, UE, PE) plus the stack fault (SF) flag are sticky bits. Once set by the processor,such a bit remains set until software clears it. For details about the causes of x87 exceptions indicatedby bits 6–0, see “x87 Floating-Point Exception Causes” on page 280.
For details about the masking ofx87 exceptions, see “x87 Floating-Point Exception Masking” on page 284.Invalid-Operation Exception (IE). Bit 0. The processor sets this bit to 1 when an invalid-operationexception occurs. These exceptions are caused by many types of errors, such as an invalid operand orby stack faults. When a stack fault causes an IE exception, the stack fault (SF) exception bit is also set.Denormalized-Operand Exception (DE). Bit 1.
The processor sets this bit to 1 when one of thesource operands of an instruction is in denormalized form. (See “Denormalized (Tiny) Numbers” onpage 255.)Zero-Divide Exception (ZE). Bit 2. The processor sets this bit to 1 when a non-zero number isdivided by zero.242x87 Floating-Point Programming24592—Rev. 3.13—July 2007AMD64 TechnologyOverflow Exception (OE). Bit 3. The processor sets this bit to 1 when the absolute value of arounded result is larger than the largest representable normalized floating-point number for thedestination format. (See “Normalized Numbers” on page 255.)Underflow Exception (UE). Bit 4. The processor sets this bit to 1 when the absolute value of arounded non-zero result is too small to be represented as a normalized floating-point number for thedestination format.
(See “Normalized Numbers” on page 255.)The underflow exception has an unusual behavior. When masked by the UM bit (bit 4 of the x87control word), the processor only reports a UE exception if the UE occurs together with a precisionexception (PE).Precision Exception (PE). Bit 5. The processor sets this bit to 1 when a floating-point result, afterrounding, differs from the infinitely precise result and thus cannot be represented exactly in thespecified destination format.
The PE exception is also called the inexact-result exception.Stack Fault (SF). Bit 6. The processor sets this bit to 1 when a stack overflow (due to a push or loadinto a non-empty stack register) or stack underflow (due to referencing an empty stack register) occursin the x87 stack-register file.
When either of these conditions occur, the processor also sets the invalidoperation exception (IE) flag, and the processor distinguishes overflow from underflow by writing thecondition-code 1 (C1) bit (C1 = 1 for overflow, C1 = 0 for underflow). Unlike the flags for the otherx87 exceptions, the SF flag does not have a corresponding mask bit in the x87 control word.If, subsequent to the instruction that caused the SF bit to be set, a second invalid-operation exception(IE) occurs due to an invalid operand in an arithmetic instruction (i.e., not a stack fault), and if softwarehas not cleared the SF bit between the two instructions, the SF bit will remain set.Exception Status (ES). Bit 7.
The processor calculates the value of this bit at each instructionboundary and sets the bit to 1 when one or more unmasked floating-point exceptions occur. If the ESbit has already been set by the action of some prior instruction, the processor invokes the #MFexception handler when the next non-control x87 or 64-bit media instruction is executed. (See“Control” on page 274 for a definition of control instructions).The ES bit can be written, but the written value is ignored. Like the SF bit, the ES bit does not have acorresponding mask bit in the x87 control word.Top-of-Stack Pointer (TOP). Bits 13–11.
The TOP contains the physical register index of thelocation of the top of stack, ST(0). It thus specifies the mapping of the x87 stack registers,ST(0)–ST(7), onto the x87 physical registers, FPR0–FPR7. The processor changes the TOP during anyinstructions that pushes or pops the stack. For details on how the stack works, see “StackOrganization” on page 240.Condition Codes (C3–C0).
Bits 14 and 10–8. The processor sets these bits according to the result ofarithmetic, compare, and other instructions. In certain cases, other status-word flags can be usedtogether with the condition codes to determine the result of an operation, including stack overflow,stack underflow, sign, least-significant quotient bits, last-rounding direction, and out-of-rangex87 Floating-Point Programming243AMD64 Technology24592—Rev.
3.13—July 2007operand. For details on how each instruction sets the condition codes, see “x87 Floating-PointInstruction Reference” in Volume 5.x87 Floating-Point Unit Busy (B). Bit 15. The processor sets the value of this bit equal to thecalculated value of the ES bit, bit 7. This bit can be written, but the written value is ignored. The bit isincluded only for backward-compatibility with the 8087 coprocessor, in which it indicates that thecoprocessor is busy.For further details about the x87 floating-point exceptions, see “x87 Floating-Point Exception Causes”on page 280.6.2.3 x87 Control Word Register (FCW)The 16-bit x87 control word register allows software to manage certain x87 processing options,including rounding, precision, and masking of the six x87 floating-point exceptions (any of which isreported as an #MF exception).
Figure 6-4 shows the format of the control word. All bits, exceptreserved bits, can be read and written.The FLDCW, FRSTOR, and FXRSTOR instructions load the control word from memory. TheFSTCW, FNSTCW, FSAVE, FNSAVE, and FXSAVE instructions store the control word to memory.The FINIT and FNINIT instructions initialize the control word with the value 037Fh, which specifiesround-to-nearest, all exceptions masked, and double-extended precision (64-bit).15 14 13 12 11 10 9YBitsMnemonic12YRCPCESSF11–109–876543210PMUMOMZMDMIMFigure 6-4.244RC8PC76res543210P U O Z D IM M M M M MDescriptionInfinity Bit (80287 compatibility)Rounding ControlPrecision ControlException StatusStack Fault#MF Exception MasksPrecision Exception MaskUnderflow Exception MaskOverflow Exception MaskZero-Divide Exception MaskDenormalized-Operand Exception MaskInvalid-Operation Exception Maskx87 Control Word Register (FCW)x87 Floating-Point Programming24592—Rev.
3.13—July 2007AMD64 TechnologyStarting from bit 0, the bits are:Exception Masks (PM, UM, OM, ZM, DM, IM). Bits 5–0. Software can set these bits to mask, orclear these bits to unmask, the corresponding six types of x87 floating-point exceptions (PE, UE, OE,ZE, DE, IE), which are reported in the x87 status word as described in “x87 Status Word Register(FSW)” on page 241. A bit masks its exception type when set to 1, and unmasks it when cleared to 0.Masking a type of exception causes the processor to handle all subsequent instances of the exceptiontype in a default way.
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