Volume 1 Application Programming (794095), страница 59
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The prefixes areignored by all other 64-bit media instructions.REX—The REX prefixes affect operands that reference a GPR or XMM register when running in64-bit mode. It allows access to the full 64-bit width of any of the 16 extended GPRs and to any ofthe 16 extended XMM registers. The REX prefix also affects the FXSAVE and FXRSTORinstructions, in which it selects between two types of 512-byte memory-image format, as describedin “Media and x87 Processor State” in Volume 2. The prefix is ignored by all other 64-bit mediainstructions.5.9.2 Special-Use and Reserved PrefixesThe following prefixes are used as opcode bytes in some 64-bit media instructions and are reserved inall other 64-bit media instructions:••Operand-Size Override—The 66h prefix.REP—The F2 and F3h prefixes.5.9.3 Prefixes That Cause ExceptionsThe following prefixes cause an exception:•LOCK—The F0h prefix causes an invalid-opcode exception when used with 64-bit mediainstructions.5.10Feature DetectionBefore executing 64-bit media instructions, software should determine whether the processor supportsthe technology by executing the CPUID instruction.
“Feature Detection” on page 74 describes howsoftware uses the CPUID instruction to detect feature support. For full support of the 64-bit mediainstructions documented here, the following features require detection:••MMX instructions, indicated by bit 23 of CPUID function 1 and function 8000_0001h.3DNow! instructions, indicated by bit 31 of CPUID function 8000_0001h.64-Bit Media Programming229AMD64 Technology••••••24592—Rev.
3.13—July 2007MMX extensions, indicated by bit 22 of CPUID function 8000_0001h.3DNow! extensions, indicated by bit 30 of CPUID function 8000_0001h.SSE instructions, indicated by bit 25 of CPUID function 8000_0001h.SSE2 instruction extensions, indicated by bit 26 of CPUID function 8000_0001h.SSE3 instruction extensions, indicated by bit 0 of CPUID function 0000_0001h.SSE4A instruction extensions, indicated by bit 6 of CPUID function 8000_0001h.Software may also wish to check for the following support, because the FXSAVE and FXRSTORinstructions execute faster than FSAVE and FRSTOR:•FXSAVE and FXRSTOR, indicated by bit 24 of CPUID function 1 and function 8000_0001h.Software that runs in long mode should also check for the following support:•Long Mode, indicated by bit 29 of CPUID function 8000_0001h.See “Processor Feature Identification” in Volume 2 for a full description of the CPUID instruction andits function codes.If the FXSAVE and FXRSTOR instructions are to be used, the operating system must support theseinstructions by having set CR4.OSFXSR = 1.
If the MMX floating-point-to-integer data-conversioninstructions (CVTPS2PI, CVTTPS2PI, CVTPD2PI, or CVTTPD2PI) are used, the operating systemmust support the FXSAVE and FXRSTOR instructions and SIMD floating-point exceptions (byhaving set CR4.OSXMMEXCPT = 1). For details, see “System-Control Registers” in Volume 2.5.11Exceptions64-bit media instructions can generate two types of exceptions:••General-Purpose Exceptions, described below in “General-Purpose Exceptions”x87 Floating-Point Exceptions (#MF), described in “x87 Floating-Point Exceptions (#MF)” onpage 231All exceptions that occur while executing 64-bit media instructions can be handled by legacyexception handlers used for general-purpose instructions and x87 floating-point instructions.5.11.1 General-Purpose ExceptionsThe sections below list exceptions generated and not generated by general-purpose instructions.
For asummary of the general-purpose exception mechanism, see “Interrupts and Exceptions” on page 86.For details about each exception and its potential causes, see “Exceptions and Interrupts” in Volume 2.Exceptions Generated. The 64-bit media instructions can generate the following general-purposeexceptions:•#DB—Debug Exception (Vector 1)23064-Bit Media Programming24592—Rev. 3.13—July 2007•••••••••AMD64 Technology#UD—Invalid-Opcode Exception (Vector 6)#DF—Double-Fault Exception (Vector 8)#SS—Stack Exception (Vector 12)#GP—General-Protection Exception (Vector 13)#PF—Page-Fault Exception (Vector 14)#MF—x87 Floating-Point Exception-Pending (Vector 16)#AC—Alignment-Check Exception (Vector 17)#MC—Machine-Check Exception (Vector 18)#XF—SIMD Floating-Point Exception (Vector 19)—Only by the CVTPS2PI, CVTTPS2PI,CVTPD2PI, and CVTTPD2PI instructions.An invalid-opcode exception (#UD) can occur if a required CPUID feature flag is not set (see “FeatureDetection” on page 229), or if an attempt is made to execute a 64-bit media instruction and theoperating system has set the floating-point software-emulation (EM) bit in control register 0 to 1(CR0.EM = 1).For details on the system control-register bits, see “System-Control Registers” in Volume 2.
For detailson the machine-check mechanism, see “Machine Check Mechanism” in Volume 2.For details on #MF exceptions, see “x87 Floating-Point Exceptions (#MF)” on page 231.Exceptions Not Generated. The 64-bit media instructions do not generate the following general-purpose exceptions:•••••••••#DE—Divide-By-Zero-Error Exception (Vector 0)Non-Maskable-Interrupt Exception (Vector 2)#BP—Breakpoint Exception (Vector 3)#OF—Overflow Exception (Vector 4)#BR—Bound-Range Exception (Vector 5)#NM—Device-Not-Available Exception (Vector 7)Coprocessor-Segment-Overrun Exception (Vector 9)#TS—Invalid-TSS Exception (Vector 10)#NP—Segment-Not-Present Exception (Vector 11)For details on all general-purpose exceptions, see “Exceptions and Interrupts” in Volume 2.5.11.2 x87 Floating-Point Exceptions (#MF)The 64-bit media instructions do not generate x87 floating-point (#MF) exceptions as a consequenceof their own computations.
However, an #MF exception can occur during the execution of a 64-bitmedia instruction, due to a prior x87 floating-point instruction. Specifically, if an unmasked x87floating-point exception is pending at the instruction boundary of the next 64-bit media instruction, the64-Bit Media Programming231AMD64 Technology24592—Rev. 3.13—July 2007processor asserts the FERR# output signal.
For details about the x87 floating-point exceptions and theFERR# output signal, see “x87 Floating-Point Exception Causes” on page 280.5.12Actions Taken on Executing 64-Bit Media InstructionsThe MMX registers are mapped onto the low 64 bits of the 80-bit x87 floating-point physical registers,FPR0–FPR7, described in “Registers” on page 238. The MMX instructions do not use the x87 stackaddressing mechanism. However, 64-bit media instructions write certain values in the x87 top-of-stackpointer, tag bits, and high bits of the FPR0–FPR7 data registers.Specifically, the processor performs the following x87-related actions atomically with the execution of64-bit media instructions:•••Top-Of-Stack Pointer (TOP)—The processor clears the x87 top-of-stack pointer (bits 13–11 in thex87 status word register) to all 0s during the execution of every 64-bit media instruction, causing itto point to the mmx0 register.Tag Bits—During the execution of every 64-bit media instruction, except the EMMS and FEMMSinstructions, the processor changes the tag state for all eight MMX registers to full, as describedbelow.
In the case of EMMS and FEMMS, the processor changes the tag state for all eight MMXregisters to empty, thus initializing the stack for an x87 floating-point procedure.Bits 79–64—During the execution of every 64-bit media instruction that writes a result to an MMXregister, the processor writes the result data to a 64-bit MMX register (the low 64 bits of theassociated 80-bit x87 floating-point physical register) and sets the exponent and sign bits (the high16 bits of the associated 80-bit x87 floating-point physical register) to all 1s. In the x87environment, the effect of setting the high 16 bits to all 1s indicates that the contents of the low 64bits are not finite numbers.
Such a designation prevents an x87 floating-point instruction frominterpreting the data as a finite x87 floating-point number.The rest of the x87 floating-point processor state—the entire x87 control-word register, the remainingfields of the status-word register, and the error pointers (instruction pointer, data pointer, and lastopcode register)—is not affected by the execution of 64-bit media instructions.The 2-bit tag fields defined by the x87 architecture for each x87 data register, and stored in the x87 tagword register (also called the floating-point tag word, or FTW), characterize the contents of the MMXregisters.
The tag bits are visible to software only after an FSAVE or FNSAVE (but not FXSAVE)instruction, as described in “Media and x87 Processor State” in Volume 2. Internally, however, theprocessor maintains only a one-bit representation of each 2-bit tag field. This single bit indicateswhether the associated register is empty or full. Table 5-6 on page 233 shows the mapping between the1-bit internal tag—which is referred to in this chapter by its empty or full state—and the 2-bitarchitectural tag.23264-Bit Media Programming24592—Rev.
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