Сигнальный МП Motorola DSP56002 (1086189), страница 51
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The program shown in Figure 6-74 begins by setting equates and then usinga JSR instruction at the receive interrupt vector location to form a long interrupt. Themain program starts by initializing pointers to the right and left data buffers. The IPR,CRA, and CRB are then initialized. The clock divider bits in the CRA do not have to beset since an external receive clock is specified (SCKD=0).
Pin SC0 is specified as an input flag (SYN=1, SCD0=0); pin SC2 is specified as TX and RX frame sync (SYN=1,SCD2=0). The SSI port is then enabled and interrupts are unmasked, which allows theMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 133Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)SSI port to begin data reception. A jump-to-self instruction is then used to hang the processor and allow interrupts to receive the data. Normally, the processor would executeuseful instructions while waiting for the receive interrupts.
When an interrupt occurs, theJSR instruction at the interrupt vector location transfers control to the RCV subroutine.The input flag is tested, and data is put in the left or right data buffer depending on theresults of the test. The RTI instruction then returns control to the main program, whichwill wait for the next interrupt.Freescale Semiconductor, Inc...;*************************************************;SSI and other I/O EQUATES*;*************************************************IPREQU$FFFFSSISR EQU$FFEECRAEQU$FFECCRBEQU$FFEDPCCEQU$FFE1RXEQU$FFEFFLGEQU$0010;*************************************************;INTERRUPT VECTOR*;*************************************************ORGP:$000CJSRRCV;*************************************************;MAIN PROGRAM*;*************************************************ORGP:$40MOVE#0,R0MOVE#$08,R1MOVE#1,M0MOVE#1,M1;Pointer to memory buffer for;received data.
Note data will be;split between two buffers which are;modulus 2.Figure 6-74 Normal Mode Receive Example (Sheet 1 of 2)6 - 134PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI);*************************************************;Initialize SSI Port*Freescale Semiconductor, Inc...;*************************************************MOVEP#$3000,X:IPRMOVEP#$4000,X:CRAMOVEP#$A300,X:CRB;Set interrupt priority register for SSI.;Set word length = 16 bits.;Enable RIE and RE; synchronous;mode with bit frame sync;;clock and frame sync are;external; SC0 is an output.;*************************************************;Init SSI Interrupt*;*************************************************ANDI#$FC,MRMOVEP#$01F8,X:PCCJMP*;Unmask interrupts.;Turn on SSI port.;Wait for interrupt.;*************************************************;MAIN INTERRUPT ROUTINE*;*************************************************RCVJSET#0,X:SSISR, RIGHTLEFTMOVEPX:RX,X:(RO)+RTIRIGHT MOVEPX:RX,X:(R1)+RTIEND;Test SCO flag.;If SCO clear, receive data;into left buffer (R0).;If SCO set, receive data;into right buffer (R1).Figure 6-74 Normal Mode Receive Example (Sheet 2 of 2)6.4.7.3Network Mode ExamplesThe network mode, the typical mode in which the DSP would interface to a TDM codecnetwork or a network of DSPs, is compatible with Bell and CCITT PCM data/operation formats.
The DSP may be a master device (see Figure 6-75) that controls its own privatenetwork or a slave device that is connected to an existing TDM network, occupying oneor more time slots. The key characteristic of the network mode is that each time slot (dataword time) is identified by an interrupt or by polling status bits, which allows the option ofignoring the time slot or transmitting data during the time slot. The receiver operates in thesame manner except that data is always being shifted into the receive shift register andtransferred to the RX. The DSP reads the receive data register and uses or discards thecontents. Overrun and underrun errors are detected.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 135Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MASTER TRANSMITMASTER RECEIVEDSP56002 MASTERDSP56002 SLAVE 1DSP56002 SLAVE 3STDSTDSTDSTDSRDSRDSRDSRDSCKSCKSCKSCKSC2TIME SLOT 1DSP56002 SLAVE 2SC2TIME SLOT 2SC2TIME SLOT 3SC2TIME SLOT 4Freescale Semiconductor, Inc...MASTER CLOCKMASTER SYNCFigure 6-75 Network Mode ExampleThe frame sync signal indicates the beginning of a new data frame.
Each data frame is divided into time slots; transmission or reception can occur in each time slot (rather than injust the frame sync time slot as in normal mode). The frame rate dividers (controlled by DC4,DC3, DC2, DC1, and DC0) control the number of time slots per frame from 2 to 32. Time-slotassignment is totally under software control. Devices can transmit on multiple time slots, receive multiple time slots, and the time-slot assignment can be changed dynamically.A simplified flowchart showing operation of the network mode is shown in Figure 6-76.Two counters are used to track the current transmit and receive time slots.
Slot counterone (SLOTCT1) is used to track the transmit time slot; slot counter two (SLOTCT2) isused for receive. When the transmitter is empty, it generates an interrupt; a test is thenmade to see if it is the beginning of a frame. If it is the beginning of a frame, SLOTCT1 iscleared to start counting the time slots. If it is not the beginning of a frame, SLOTCT1 isincremented.
The next test checks to see if the SSI should transmit during this time slot.If it is time to transmit, data is written to the TX; otherwise, dummy data is written to theTSR, which prevents a transmit underrun error from occurring and three-states the STDpin. The DSP can then return to what it was doing before the interrupt and wait for the nextinterrupt to occur. SLOTCT1 should reflect the data in the shift registers to coincide withTFS. Software must recognize that the data being written to TX will be transmitted in timeslot SLOTCT1 plus one.6 - 136PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLAFor More Information On This Product,Go to: www.freescale.comPORT CWRITE DATATO TXYESCLEAR SLOTNUMBERSLOTCT1YESEXITWRITEDUMMY DATATO TSRNOINCREMENT SLOT NUMBERSLOTCT1 = SLOTCT1 + 1NOKEEP DATAYESCLEAR SLOTNUMBERSLOTCT2 = 0YESFigure 6-76 TDM Network Software FlowchartMY TURNTO TRANSMIT?SLOTCT1 =MYSLOT?TEST FORFRAME SYNCTFS = 1?TRANSMITTEREMPTYINTERRUPTEXITIS DATAFOR ME?SLOTCT2 =MYSLOT?TEST FORFRAME SYNCRFS = 1?READ DATAFROM RXRECEIVERFULLINTERRUPTFreescale Semiconductor, Inc...NODISCARDDATAINCREMENT SLOT NUMBERSLOTCT2 = SLOTCT2 + 1NOFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)6 - 137Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...The receiver operates in a similar manner.
When the receiver is full, an interrupt is generated, and a test is made to see if this is the beginning of a frame. If it is the beginning ofa frame, SLOTCT2 is cleared to start counting the time slots. If it is not the beginning of aframe, SLOTCT2 is incremented. The next test checks to see if the data received is intended for this DSP. If the current time slot is the one assigned to the DSP receiver, thedata is kept; otherwise, the data is discarded, and the DSP can then return to what it wasdoing before the interrupt. SLOTCT2 should reflect the data in the receive shift register tocoincide with the RFS flag.
Software must recognize that the data being read from RX isfor time slot SLOTCT2 minus two.Initializing the network mode is accomplished by setting the bits in CRA and CRB as follows (see Figure 6-77):1. The word length must be selected by setting WL1 and WL0. In this example,an 8-bit word length was chosen (WL1=0 and WL0=0).2. The number of time slots is selected by setting DC4–DC0. Four time slotswere chosen for this example (DC4–DC0=$03).3. The serial clock rate must be selected by setting PSR and PM7–PM0 (seeTable 6-15 (a), Table 6-15 (b), and Table 6-16).4.RE and TE must be set to activate the transmitter and receiver.
If interruptsare to be used, RIE and TIE should be set. RIE and TIE are usually set aftereverything else is configured and the DSP is ready to receive interrupts.5. The network mode must be selected (MOD=1).6. A continuous clock is selected in this example by setting GCK=0.7. Although it is not required for the network mode, synchronous clock controlwas selected (SYN=1).8. The frame sync length was chosen in this example as word length (FSL1=0)for both transmit and receive frame sync (FSL0=0). Any other combinationscould have been selected, depending on the application.9.
Control bits SHFD, SCKD, SCD2, SCD1, SCD0, and the flag bits (OF1 andOF0) should be set as needed for the application.6 - 138PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)SSI CONTROL REGISTER A (CRA)(READ/WRITE)X:$FFEC151413121110PSR00000WL1WL0DC4DC38-BIT WORD LENGTH981DC21DC176543210PM7PM6PM5PM4PM3PM2PM1PM06543210SCD2SCD1SCD0OF1OF0DC0FOUR TIME SLOTSFreescale Semiconductor, Inc...SSI CONTROL REGISTER B (CRB)(READ/WRITE)X:$FFED15141312RIETIERETE111098710100SHFD SCKDSCD2SERIAL CONTROL 2 DIRECTION1 = OUTPUT (MASTER)0 = INPUT (SLAVE)MODSSI MODE SELECT1 = NETWORKGCKGATED CLOCK CONTROL0 = CONTINUOUS CLOCKSCKDCLOCK SOURCE DIRECTION1 = OUTPUT (MASTER)0 = INPUT (SLAVE)SYNSYNC/ASYNC CONTROL1 = SYNCHRONOUSFLS0FRAME SYNC LENGTH 00 =TX, RX SYNC SAME LENGTHFSL1FRAME SYNC LENGTH 10 = WORD WIDTH76543210X:$FFEERDFTDEROETUERFSTFSIF1IF0X:$FFEE********SSI STATUS REGISTER (SR)(READ)SSI TIME SLOT REGISTER B (TSR)(WRITE)SERIALCLOCKFRAMESYNCINTERNAL TX FLAGS AND INTERRUPTSSERIAL DATA4SLOT 1SLOT 2SLOT 3SLOT 4SLOT 1SINTERNAL RX FLAGS AND INTERRUPTSFigure 6-77 Network Mode InitializationMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 139Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)6.4.7.3.1Network Mode TransmitWhen TE is set, the transmitter will be enabled only after detection of a new data framesync.
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