Сигнальный МП Motorola DSP56002 (1086189), страница 48
Текст из файла (страница 48)
SSI Receive Data with Exception Status – occurs when the receive interrupt isenabled, the receive data register is full, and a receiver overrun error hasoccurred. ROE is cleared by first reading the SSISR and then reading RX.3. SSI Transmit Data – occurs when the transmit interrupt is enabled, the transmit data register is empty, and no transmitter error conditions exist. Writing toTX or the TSR will clear this interrupt. This error-free interrupt may use a fastinterrupt service routine for minimum overhead.4.
SSI Transmit Data with Exception Status – occurs when the transmit interruptis enabled, the transmit data register is empty, and a transmitter underrunerror has occurred. TUE is cleared by first reading the SSISR and then writingto TX or the TSR to clear the pending interrupt.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 109Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)EXCEPTIONSTARTINGADDRESSPROGRAM MEMORY SPACEFreescale Semiconductor, Inc...EXCEPTION SOURCETWO WORDS PER VECTOR$0000HARDWARE RESET$0002STACK ERROR$0004TRACE$0006SWI (SOFTWARE INTERRUPT)$0008IRQA EXTERNAL HARDWARE INTERRUPTEXTERNAL INTERRUPTSINTERNALINTERRUPTS$000AIRQB EXTERNAL HARDWARE INTERRUPT$000CSSI RECEIVE DATA$000ESSI RECEIVE DATA WITH EXCEPTION STATUS$0010SSI TRANSMIT DATA$0012SSI TRANSMIT DATA WITH EXCEPTION STATUS$0014SCI RECEIVE DATA$0016SCI RECEIVE DATA WITH EXCEPTION STATUS$0018SCI TRANSMIT DATA$001ASCI IDLE LINE$001CSCI TIMER$001ERESERVED$0020HOST RECEIVE DATA$0022HOST TRANSMIT DATA$0024HOST COMMAND (DEFAULT)$0026AVAILABLE FOR HOST COMMAND$0028AVAILABLE FOR HOST COMMANDAVAILABLE FOR HOST COMMAND$003CTIMER$003EILLEGAL INSTRUCTION$0040AVAILABLE FOR HOST COMMAND$007EAVAILABLE FOR HOST COMMANDSYNCHRONOUSSERIALINTERFACEINTERNALINTERRUPTS•••$003AEXTERNALINTERRUPTSSERIALCOMMUNICATIONSINTERFACEHOSTINTERFACEINTERNALINTERRUPTS•••Figure 6-53 SSI Exception Vector Locations6 - 110PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)RECEIVEINTERRUPT SERVICE ROUTINESSI CONTROL REGISTER (CRB)(READ/WRITE)X:$FFED15141312111098RIETIERETEMODGCKSYNFSL11.
INTERRUPT IS GENERATED WHENRIE = 1, RDF = 1, AND ROE = 0.2. PENDING INTERRUPT IS CLEAREDBY READING RX.Freescale Semiconductor, Inc...SSIEXCEPTIONMASKRECEIVE WITH EXCEPTION STATUSINTERRUPT SERVICE ROUTINE1. INTERRUPT IS GENERATED WHENRIE = 1, RDF = 1, AND ROE = 1.SSI EXCEPTION MASKEXCEPTIONSTARTINGADDRESS2.
ROE IS CLEARED BY READINGSSISR FOLLOWED BY:EXCEPTION VECTOR TABLE$00003. READING RX TO CLEAR PENDINGINTERRUPT.4. APPLICATION-SPECIFIC CODE.$000C SSI RECEIVE DATA$000E SSI RECEIVE DATA WITH EXCEPTIONS STATUSTRANSMITINTERRUPT SERVICE ROUTINE$0010 SSI TRANSMIT DATA$0012 SSI TRANSMIT DATA WITH EXCEPTION STATUS1. INTERRUPT IS GENERATED WHENTIE = 1, TDF = 1, AND TUE = 0.2. PENDING INTERRUPT IS CLEAREDBY WRITING TO TX OR TSR.SSI STATUS REGISTER (SSISR)(READ ONLY)X:$FFFE76543210RDFTDEROETUERFSTFSIF1IF0SSI STATUS BITSTRANSMIT WITH EXCEPTION STATUSINTERRUPT SERVICE ROUTINE1. INTERRUPT IS GENERATED WHENTIE = 1, TDF = 1, AND TUE = 1.2.
TUE IS CLEARED BY READINGSSISR FOLLOWED BY:3. WRITING TO TX OR TSR TO CLEARPENDING INTERRUPT.4. APPLICATION-SPECIFIC CODE.Figure 6-54 SSI ExceptionsMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 111Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Table 6-17 SSI Operating ModesFreescale Semiconductor, Inc...OperatingFormatSerialClockTX, RXSectionsTypical ApplicationsNormalContinuous Asynchronous Single Asynchronous Codec; Stream-Mode Channel InterfaceNormalContinuous SynchronousMultiple Synchronous CodecsNormalGatedAsynchronousDSP-to-DSP; Serial Peripherals (A/D,D/A)NormalGatedSynchronousSPI-Type Devices; DSP to MCUNetworkContinuous AsynchronousTDM NetworksNetworkContinuous SynchronousTDM Codec Networks, TDM DSP NetworksOn DemandGatedAsynchronousParallel-to-Serial and Serial-to-Parallel ConversionOn DemandGatedSynchronousDSP to SPI Peripherals6.4.7Operating Modes – Normal, Network, and On-DemandThe SSI has three basic operating modes and many data/operation formats.
Thesemodes can be programmed by several bits in the SSI control registers. Table 6-17 liststhe SSI operating modes and some of the typical applications in which they may be used.The data/operation formats are selected by choosing between gated and continuousclocks, synchronization of transmitter and receiver, selection of word or bit frame sync,and whether the LSB is transferred first or last. The following paragraphs describe how toselect a particular data/operation format and describe examples of normal-mode and network-mode applications. The on-demand mode is selected as a special case of the network mode.The SSI can function as an SPI master or SPI slave, using additional logic for arbitration,which is required because the SSI interface does not perform SPI master/slave arbitration.
An SPI master device always uses an internally generated clock; whereas, an SPIslave device always uses an external clock.6.4.7.1Data/Operation FormatsThe data/operation formats available to the SSI are selected by setting or clearing controlbits in the CRB. These control bits are MOD, GCK, SYN, FSL1, FSL0, and SHFD.6.4.7.1.1Normal/Network Mode SelectionSelecting between the normal mode and network mode is accomplished by clearing or setting the MOD bit in the CRB (see Figure 6-55).
For normal mode, the SSI functions with onedata word of I/O per frame (see Figure 6-56). For the network mode, 2 to 32 data words of6 - 112PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...I/O may be used per frame. In either case, the transfers are periodic. The normal mode istypically used to transfer data to/from a single device.
Network mode is typically used in timedivision multiplexed (TDM) networks of codecs or DSPs with multiple words per frame (seeFigure 6-57, which shows two words in a frame with either word-length or bit-length framesync). The frame sync shown in Figure 6-55 is the word-length frame sync.
A bit-lengthframe sync can be chosen by setting FSL1 and FSL0 for the configuration desired.6.4.7.1.2Continuous/Gated Clock SelectionThe TX and RX clocks may be programmed as either continuous or gated clock signalsby the GCK bit in the CRB. A continuous TX and RX clock is required in applications suchas communicating with some codecs where the clock is used for more than just datatransfer.
A gated clock, in which the clock only toggles while data is being transferred, isuseful for many applications and is required for SPI compatibility. The frame sync outputsmay be used as a start conversion signal by some A/D and D/A devices.Figure 6-58 illustrates the difference between continuous clock and gated clock systems.A separate frame-sync signal is required in continuous clock systems to delimit the activeclock transitions. Although the word-length frame sync is shown in Figure 6-58, abit-length frame sync can be used (see Figure 6-59). In gated clock systems, frame synchronization is inherent in the clock signal; thus a separate sync signal is not required (seeFigure 6-60 and Figure 6-61).
The SSI can be programmed to generate frame sync outputs in gated clock mode but does not use frame sync inputs.Input flags (see Figure 6-60 and Figure 6-61) are latched on the negative edge of the firstdata bit of a frame. Output flags are valid during the entire frame.6.4.7.1.3Synchronous/Asynchronous Operating ModesThe transmit and receive sections of this interface may be synchronous or asynchronous– i.e., the transmitter and receiver may use common clock and synchronization signals(synchronous operating mode, see Figure 6-62) or they may have their own separateclock and sync signals (asynchronous operating mode).
The SYN bit in CRB selects synchronous or asynchronous operation. Since the SSI is designed to operate either synchronously or asynchronously, separate receive and transmit interrupts are provided.Figure 6-63 illustrates the operation of the SYN bit in the CRB. When SYN equals zero, theSSI TX and RX clocks and frame sync sources are independent. If SYN equals one, the SSITX and RX clocks and frame sync come from the same source (either external or internal).MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 1136 - 114DATATIERIETE12For More Information On This Product,Go to: www.freescale.comPORT CSLOT 1SYN9FSL18FSL07* NORMAL MOD = 0GCK10* NETWORK MOD = 1SLOT 3RECEIVER INTERRUPT AND FLAGS SETSLOT 2SHFD6RECEIVER INTERRUPT AND FLAGS SETTRANSMITTER INTERRUPTS AND FLAGS SETSLOT 1DATASCKD5SCD24Figure 6-55 CRB MOD Bit OperationNOTE: Interrupts occur every time slot and a word may be transferred.SERIAL DATAFRAME SYNCSERIAL CLOCK*MOD11TRANSMITTER INTERRUPT AND FLAGS SETRE13NOTE: Interrupts occur and data is transferred once per frame sync.SERIAL DATAFRAME SYNCSERIAL CLOCKX:$FFED1415SCD13SLOT 2SCD02Freescale Semiconductor, Inc...OF11OF00SSI CONTROL REGISTER B (CRB)(READ/WRITE)Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)FRAME SYNC(FSL0 = 0, FSL1 = 0)FRAME SYNC(FSL0 = 0, FSL1 = 1)Freescale Semiconductor, Inc...DATA OUTFLAGSSLOT 0WAITSLOT 0Figure 6-56 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)FRAME SYNC(FSL0 = 0, FSL1 = 0)FRAME SYNC(FSL0 = 0, FSL1 = 1)DATAFLAGSSLOT 0SLOT 1SLOT 0SLOT 1Figure 6-57 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 1156 - 116TIERIEDATARE13TE12For More Information On This Product,Go to: www.freescale.comPORT CDATAMOD11SYN9FSL18FSL07SHFD6SCKD5SCD24* GATED CLOCK GCK = 1SCD13DATADATA STABLEDATA CHANGESDATADATA STABLEDATA CHANGES* CONTINUOUS CLOCK GCK = 0*GCK10Figure 6-58 CRB GCK Bit OperationNOTES:1.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
