Сигнальный МП Motorola DSP56002 (1086189), страница 45
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OF0 andOF1 are double buffered so that the flag states appear on the pins when the TX data istransferred to the transmit shift register (i.e., the flags are synchronous with the data).Hardware and software reset clear OF1.Note: The optional serial output pins (SC0, SC1, and SC2) are controlled by the frametiming and are not affected by TE or RE.6.4.2.2.3CRB Serial Control 0 Direction (SCD0) Bit 2SCD0 controls the direction of the SC0 I/O line. When SCD0 is cleared, SC0 is an input;when SCD0 is set, SC0 is an output (see Tables Table 6-5 and Table 6-6, and Figure6-46).
Hardware and software reset clear SCD0.6.4.2.2.4CRB Serial Control 1 Direction (SCD1) Bit 3SCD1 controls the direction of the SC1 I/O line. When SCD1 is cleared, SC1 is an input;when SCD1 is set, SC1 is an output (see Tables Table 6-5 and Table 6-6 and Figure6-46). Hardware and software reset clear SCD1.6.4.2.2.5CRB Serial Control 2 Direction (SCD2) Bit 4SCD2 controls the direction of the SC2 I/O line.
When SCD2 is cleared, SC2 is an input;when SCD2 is set, SC2 is an output (see Tables Table 6-5 and Table 6-6, and Figure6-46). Hardware and software reset clear SCD2.6.4.2.2.6CRB Clock Source Direction (SCKD) Bit 5SCKD selects the source of the clock signal used to clock the transmit shift register in theasynchronous mode and both the transmit shift register and the receive shift register inthe synchronous mode. When SCKD is set, the internal clock source becomes the bitclock for the transmit shift register and word length divider and is the output on the SCKpin.
When SCKD is cleared, the clock source is external; the internal clock generator isdisconnected from the SCK pin, and an external clock source may drive this pin. Hardware and software reset clear SCKD.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 896 - 90X:$FFEDFor More Information On This Product,Go to: www.freescale.comPORT CTERESC0SC1SC2SCKSRDSTD1213MOD11GCK10FSL18FSL07SCD0SCD1SCD2SCKD——DIRECTIONCONTROLLED BYSYN9SCD2(0)SCKD(0)SCD1(0)3SCD0(0)2BASIC FUNCTION1 = OUTPUT0 = INPUT45OF110OF0RECEIVE CLOCK/FLAG 0RECEIVE FRAME SYNC/FLAG 1TRANSMIT FRAME SYNC/TX AND RX FRAME SYNCTRANSMIT CLOCK/TX AND RX CLOCKSSI RECEIVE DATASSI TRANSMIT DATASHFD6Figure 6-46 Serial Control, Direction BitsNOTE: Parentheses indicate RESET condition.CTIERIEPORT1415Freescale Semiconductor, Inc...SSI CONTROL REGISTER B (CRB)(READ/WRITE)Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.2.2.7CRB Shift Direction (SHFD) Bit 6This bit causes the transmit shift register to shift data out MSB first when SHFD equalszero or LSB first when SHFD equals one.
Receive data is shifted in MSB first when SHFDequals zero or LSB first when SHFD equals one. Hardware reset and software reset clearSHFD.6.4.2.2.8CRB Frame Sync Length (FSL0 and FSL1) Bits 7 and 8These bits select the type of frame sync to be generated or recognized (see Table 6-11).If FSL1 equals zero and FSL0 equals zero, a word-length frame sync is selected for bothTX and RX that is the length of the data word defined by bits WL1 and WL0. If FSL1 equalsone and FSL0 equals zero, a 1-bit clock period frame sync is selected for both TX and RX.When FSL0 equals one, the TX and RX frame syncs are different lengths.
Hardware resetand software reset clear FSL0 and FSL1.Table 6-11 Frame Sync LengthFSL1FSL0Frame Sync Length00WL bit clock for both TX/RX01One-bit clock for TX and WL bit clock for RX10One-bit clock for both TX/RX11One-bit clock for RX and WL bit clock for TX6.4.2.2.9CRB Sync/Async (SYN) Bit 9SYN controls whether the receive and transmit functions of the SSI occur synchronouslyor asynchronously with respect to each other. When SYN is cleared, asynchronous modeis chosen and separate clock and frame sync signals are used for the transmit and receivesections. When SYN is set, synchronous mode is chosen and the transmit and receivesections use common clock and frame sync signals.
Hardware reset and software resetclear SYN.6.4.2.2.10CRB Gated Clock Control (GCK) Bit 10GCK is used to select between a continuously running data clock or a clock that runs onlywhen there is data to be sent in the transmit shift register. When GCK is cleared, a continuous clock is selected; when GCK is set, the clock will be gated.
Hardware reset andsoftware reset clear GCK.Note: For gated clock mode with externally generated bit clock, internally generatedframe sync is not defined.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 91Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.2.2.11CRB SSI Mode Select (MOD) Bit 11MOD selects the operational mode of the SSI. When MOD is cleared, the normal mode isselected; when MOD is set, the network mode is selected. In the normal mode, the framerate divider determines the word transfer rate – one word is transferred per frame syncduring the frame sync time slot.
In network mode, a word is (possibly) transferred everytime slot. For more details, see 6.4.3. Hardware and software reset clear MOD.6.4.2.2.12CRB SSI Transmit Enable (TE) Bit 12TE enables the transfer of data from TX to the transmit shift register. When TE is set anda frame sync is detected, the transmit portion of the SSI is enabled for that frame. WhenTE is cleared, the transmitter will be disabled after completing transmission of data currently in the SSI transmit shift register. The serial output is three-stated, and any datapresent in TX will not be transmitted (i.e., data can be written to TX with TE cleared; TDEwill be cleared, but data will not be transferred to the transmit shift register).The normal mode transmit enable sequence is to write data to TX or TSR before settingTE.
The normal transmit disable sequence is to clear TE and TIE after TDE equals one.In the network mode, the operation of clearing TE and setting it again will disable thetransmitter after completing transmission of the current data word until the beginning ofthe next frame. During that time period, the STD pin will remain in the high-impedancestate.
Hardware reset and software reset clear TE.The on-demand mode transmit enable sequence can be the same as the normal mode,or TE can be left enabled.Note: TE does not inhibit TDE or transmitter interrupts. TE does not affect the generationof frame sync or output flags.6.4.2.2.13CRB SSI Receive Enable (RE) Bit 13When RE is set, the receive portion of the SSI is enabled. When this bit is cleared, thereceiver will be disabled by inhibiting data transfer into RX.
If data is being received whilethis bit is cleared, the remainder of the word will be shifted in and transferred to the SSIreceive data register.RE must be set in the normal mode and on-demand mode to receive data. In networkmode, the operation of clearing RE and setting it again will disable the receiver after reception of the current data word until the beginning of the next data frame.
Hardware andsoftware reset clear RE.Note: RE does not inhibit RDF or receiver interrupts. RE does not affect the generation6 - 92PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)of a frame sync.Freescale Semiconductor, Inc...6.4.2.2.14CRB SSI Transmit Interrupt Enable (TIE) Bit 14The DSP will be interrupted when TIE and the TDE flag in the SSI status register is set.(In network mode, the interrupt takes effect in the next frame synch, not in the next timeslot.) When TIE is cleared, this interrupt is disabled. However, the TDE bit will always indicate the transmit data register empty condition even when the transmitter is disabledwith the TE bit. Writing data to TX or TSR will clear TDE, thus clearing the interrupt.
Hardware and software reset clear RE.There are two transmit data interrupts that have separate interrupt vectors:1. Transmit data with exceptions – This interrupt is generated on the followingcondition:TIE=1, TDE=1, and TUE=12. Transmit data without exceptions – This interrupt is generated on the followingcondition:TIE=1, TDE=1, and TUE=0See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more information on exceptions.6.4.2.2.15CRB SSI Receive Interrupt Enable (RIE) Bit 15When RIE is set, the DSP will be interrupted when RDF in the SSI status register is set.(In network mode, the interrupt takes effect in the next frame synch, not in the next timeslot.) When RIE is cleared, this interrupt is disabled.
However, the RDF bit still indicatesthe receive data register full condition. Reading the receive data register will clear RDF,thus clearing the pending interrupt. Hardware and software reset clear RIE.There are two receive data interrupts that have separate interrupt vectors:1.
Receive data with exceptions – This interrupt is generated on the followingcondition:RIE=1, RDF=1, and ROE=12. Receive data without exceptions – This interrupt is generated on the followingcondition:RIE=1, RDF=1, and ROE=0See SECTION 7 PROCESSING STATES in the DSP56000 Family Manual for more information on exceptions.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 93Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.2.3SSI Status Register (SSISR)The SSISR is an 8-bit read-only status register used by the DSP to interrogate the statusand serial input flags of the SSI.
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