Сигнальный МП Motorola DSP56002 (1086189), страница 40
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Each processor in this system has one address that it responds to although each processor can be programmed to respond to more than one address.6.3.8.3Idle Line WakeupA wakeup mode frees a DSP from reading messages intended for other processors. Theusual operational procedure is for each DSP to suspend SCI reception (the DSP can continue processing) until the beginning of a message.
Each DSP compares the address inthe message header with the DSPs address. If the addresses do not match, the SCI againsuspends reception until the next address. If the address matches, the DSP will read andprocess the message and then suspend reception until the next address.The idle line wakeup mode wakes up the SCI to read a message before the first characterarrives. This mode allows the message to be in any format.Figure 6-32 shows how to configure the SCI to detect and respond to an idle line. Theword format chosen (WDS2, WDS1, and WDS0 in the SCR) must be asynchronous.
TheWAKE bit must be clear to select idle line wakeup, and RWU must be set to put the SCIto “sleep” and enable the wakeup function. RIE should be set if interrupts are to be usedto receive data. If processing must occur when the idle line is first detected, ILIE shouldbe set. The current message is followed by one or more data frames of ones (10 or 11 bitseach, depending on which word format is used), which are detected as an idle line. If theword format is multidrop (an 11-bit code), after the 11 ones, the receiver determines theline is idle and (1) clears the RWU, enabling the receiver. The IDLE bit (2) and an internalflag SRIINT (3) are set, indicating the line is idle.
The SCI is now ready to receive messages; however, nothing more will happen until the next start bit unless (4) ILIE is set.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 576 - 58For More Information On This Product,Go to: www.freescale.comPORT CX:$FFF3X:$FFF4X:$FFF5X:$FFF6X:$FFF3X:$FFF4X:$FFF5X:$FFF623232323STXSTX16 158 78 78 78 7“A”STXASTXSTXASTX0000IDLE LINEADDRESSIDLE LINESTST1100SCI TRANSMIT DATA REGISTER (WRITE ONLY)TXDTXD00SCI TRANSMIT DATA REGISTER LOW (WRITE ONLY)SCI TRANSMIT DATA REGISTER MID (WRITE ONY)SCI TRANSMIT DATA REGISTER HIGH (WRITE ONLY)DATA00Figure 6-30 Transmitting Data and Address CharactersSCI TRANSMIT DATA SHIFT REGISTERSTX16 1516 15SCI TRANSMIT DATA SHIFT REGISTERSTX16 15“A”$4101000001Freescale Semiconductor, Inc...0000111DATA0STOP STNEXTCHARACTERSTOP STADDRESS00NEXTCHARACTERFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAMOTOROLARECA2 MESSAGE AXMITDSP56002SCI PORTADDRESS 1STIRSCKPFor More Information On This Product,Go to: www.freescale.comPORT CIDLE13N0RIE11IDLEN1RECN4ADDRESS NN3N5FIRST CHARACTERN6WOMS17XMITN71RWU6D0SBK4D2D3D4XMITD5WDS000D60AND1SECOND CHARACTEROF MESSAGE DD0THIRD CHARACTERMESSAGE D1KSCI CONTROL REGISTER (SCR)(READ/WRITE)INDICATES A DATA CHARACTERD7RECDSP56002SCI PORTADDRESS NWDS111SECOND CHARACTERA1 MESSAGE BRECWDS212FIRST CHARACTER OF MESSAGE DD1XMIT3SSFTDDSP56002SCI PORTADDRESS N-1WAKE5Figure 6-31 Wired-OR ModeRECOTHERSERIAL PORTADDRESS 3RE8A3 MESSAGE CTE9INDICATES AN ADDRESS CHARACTERN210ILIEDSP56002SCI PORTADDRESS 2XMITTIE12IDLE LINE WAKEUPAND/OR INTERRUPTTMIEADDRESS CHARACTER WAKEUPAND/OR INTERRUPTX:$FFF01415Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)6 - 596 - 60STIRSCKPMESSAGE AA1TE9RE8WOMS7RWU16WAKE05A2SBK4For More Information On This Product,Go to: www.freescale.comPORT CFER8PE5OR410(READ ONLY)1Figure 6-32 Idle Line WakeupSCI IDLE LINEINTERRUPTVECTORTABLEMESSAGE BP:$001ARDRF TDRE TRNE SCI STATUS REGISTER (SSR)2IDLE (SRIINT)134.
IF ILIE = 1 IN SCR, THEN AN SCI IDLE LINE INTERRUPT IS PENDING.5. WHEN IDLE LINE INTERRUPT IS ACCEPTED, SRIINT IS AUTOMATICALLY CLEARED.X:$FFF1672SSFTD WDS2 WDS131. RWU IS CLEARED; THE RECEIVER IS ENABLED.2. IDLE IS SET IN SSR, INDICATING THE LINE IS IDLE.3. AN INTERNAL FLAG SRIINT IS GENERATED ONCE EACH IDLE STATE, NO MATTER HOW LONG IT LASTS.ILIERIE101111TIE12TMIE13LINE IS IDLE FOR 10 OR 11 STOP BITSX:$FFF014150WDS0Freescale Semiconductor, Inc...IDLE LINEINTERRUPT SERVICEROUTINE(FAST OR LONG)SCI CONTROL REGISTER (SCR)(READ/WRITE)Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)If ILIE is set, an SCI idle line interrupt will be recognized as pending.
When the idle lineMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...interrupt is recognized (5), SRIINT is automatically cleared, and the SCI waits for the firststart bit of the next character. Since RIE was set, when the first character is received, anSCI receive data interrupt (or SCI receive data with exception status interrupt if an erroris detected) will be recognized as pending. When the receiver has processed the message and is ready to wait for another idle line, RWU must be set to one again.6.3.8.4Address Mode WakeupThe purpose and basic operational procedure for address mode wakeup is the same asidle line wakeup.
The difference is that address mode wakeup re-enables the SCI whenthe ninth bit in a character is set to one (if cleared, this bit marks a character as data; ifset, an address). As a result, an idle line is not needed, which eliminates the dead timebetween messages. If the protocol is such that the address byte is not needed or is notwanted in the first byte of the message, a data byte can be written to STXA at the beginning of each message. It is not essential that the first byte of the message contain an address; it is essential that the start of a new message is indicated by setting the ninth bit toone using STXA.Figure 6-33 shows how to configure the SCI to detect and respond to an address character.
The word format chosen (WDS2, WDS1, and WDS0 in the SCR) must be an asynchronous word format. The WAKE bit must be set to select address mode wakeup andRWU must be set to put the SCI to “sleep” and enable the wakeup function. RIE shouldbe set if interrupts are to be used to receive data. (1) When an address character (ninthbit=1) is received, then R8 is set to one in the SSR, and RWU is cleared. Clearing RWUre-enables the SCI receiver. Since (2) RIE was set in this example, when the first character is received, an SCI receive data interrupt (or SCI receive data with exception statusinterrupt if an error is detected) will be recognized as pending. When the receiver is readyto wait for another address character, RWU must be set to one again.6.3.8.5Multidrop ExampleThe program shown in Figure 6-34 configures the SCI as a multidrop master transmitterand slave receiver (using wakeup on address bit) that uses interrupts to transmit data froma circular buffer and to receive data into a different circular buffer.
This program can be runwith the I/O pins (RXD and TXD) connected and with a pullup resistor for test purposes.The program starts by setting equates for convenience and clarity and then pointsthe reset vector to the start of the program. The receive and transmit interrupt vector locations have JSRs forming long interrupts because the multidrop protocol andcircular buffers require more than two instructions for maintenance. Byte packingand unpacking are not used in this example. The SRX and STX registers are equated to $FFF4, causing only the LSB of the 24-bit DSP word to be used for SCI data.The SCI is then initialized as wired-OR, multidrop, and using interrupts.
The SCIMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 616 - 62STIRSCKPA1TMIE13111A2RIEMESSAGE ATIE12TE9MESSAGE BILIE10A3RE8MESSAGE CWOMS7A4RWU16SBK4MESSAGE DWAKE152SSFTD WDS23For More Information On This Product,Go to: www.freescale.comPORT CR81FEPEOR1RDRF TDRE TRNE0Figure 6-33 Address Mode WakeupP:$0014SCI STATUS REGISTER (SSR)(READ ONLY)2. IF RIE = 1 IN SCR, THEN AN SCI RECEIVE DATA INTERRUPT IS PROCESSED.70WDS1 WDS01SCI RECEIVE DATAINTERRUPTVECTORTABLE1.
WHEN ADDRESS CHARACTER IS RECEIVED, THEN R8 = 1 IN SSR AND RWU IS CLEARED. THE RECEIVER WAKES UP.X:$FFF1X:$FFF01415Freescale Semiconductor, Inc...RECEIVE DATAINTERRUPT SERVICEROUTINE(FAST OR LONG)SCI CONTROL REGISTER (SCR)(READ/WRITE)Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)is enabled but the interrupts are masked, which prevents the SCI from transmittingor receiving data at this time.Freescale Semiconductor, Inc...The circular buffers used have two pointers. The first points to the first data byte; the second points to the last data byte. This configuration allows the transmit buffer to act as afirst-in first-out (FIFO) memory. The FIFO can be loaded by a program and emptied by theSCI in real time.
As long as the number of data bytes never exceeds the buffer size, therewill be no overflow or underflow of the buffer. Registers M0-M3 must be loaded with thebuffer size minus one to make pointer registers R0-R3 work as circular pointers. RegisterN2 is used as a constant to clear the receive buffer empty flag.The main program starts by filling the transmit buffer with a data packet.
When the transmit buffer is full, it calls the subroutine that transmits the slave’s address and then jumpsto self (SEND jmp SEND), allowing interrupts to transmit and receive the data.The receive subroutine first checks each byte to see if it is address or data. If it is an address, it compares the address with its own. If the addresses do not match, the SCI is putback to sleep. If the addresses match, the SCI is left awake, and control is returned to themain program. If the byte is data, it is placed in the receive buffer, and the receive bufferempty flag is cleared.
Although this flag is not used in this program, it can be used by another program as a simple test to see if data is available. Using N2 as the constant $0allows the flag to be cleared with a single-word instruction, which can be part of a fast interrupt.The transmit subroutine transmits a byte and then checks to see if the transmit buffer isempty. If the buffer is not empty, control is returned to the main program, and interruptsare allowed to continue emptying the buffer. If the buffer is empty, the transmit buffer empty flag is set, the transmit interrupt is disabled, and control is returned to the main program.The wakeup subroutine transmits the slave’s address by writing the address to the STXAregister and by enabling the transmit interrupt to allow interrupts to empty the transmitbuffer.
Control is then returned to the main program.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 63Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI);*******************************************************************************************;MULTIDROP MASTER/SLAVE WITH INTERRUPTS AND CIRCULAR BUFFERS*Freescale Semiconductor, Inc...;*******************************************************************************************;*************************************************;SCI and other EQUATES*;*************************************************STARTEQU$0040;Start of programTX_BUFFEQU$0010;Transmit buffer locationRX_BUFFEQU$0020;Receive buffer locationB_SIZEEQU$000E;Transmit and receive buffer size;(don’t allow the TX buffer and RX;buffers to overlap).TX_MTYEQU$0000;Transmit buffer emptyRX_MTYEQU$0001;Receive buffer emptyPCCEQU$FFE1;Port C control registerSCREQU$FFF0;SCI interface control registerSCCREQU$FFF2;SCI clock control registerSTXAEQU$FFF3;SCI transmit address registerSRXEQU$FFF4;SCI receive registerSTXEQU$FFF4;SCI transmit registerBCREQU$FFFE;Bus control registerIPREQU$FFFF;Interrupt priority register;*************************************************;RESET VECTOR*;*************************************************ORGP:$0000JMPSTART;*************************************************;SCI RECEIVE INTERRUPT VECTOR*;*************************************************ORGP:$0014;Load the SCI RX interrupt vectorsJSRRX;Jump to the receive routine that puts;data packet in a circular buffer if it is for;this address.NOP;Second word of fast interrupt not neededFigure 6-34 Multidrop Transmit Receive Example (Sheet 1 of 4)6 - 64PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI);This interrupt occurs when data is;received with errors.
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