Сигнальный МП Motorola DSP56002 (1086189), страница 35
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The maximum 1 × clock is the crystal frequency divided by 8.9.For the synchronous mode, the clock is gated.10.For both the asynchronous and synchronous modes, the transmitter andreceiver are synchronous with each other.6.3.2.3.1SCCR Clock Divider (CD11–CD0) Bits 11–0The clock divider bits (CD11–CD0) are used to preset a 12-bit counter, which is decremented at the Icyc rate (crystal frequency divided by 2). The counter is not accessible tothe user. When the counter reaches zero, it is reloaded from the clock divider bits. Thus,a value of 0000 0000 0000 in CD11–CD0 produces the maximum rate of Icyc, and a valueof 0000 0000 0001 produces a rate of Icyc/2.
The lowest rate available is Icyc/4096. Figure6-12 and Figure 6-35 show the clock dividers. Bits CD11–CD0 are cleared by hardwareand software reset.SELECT 8-OR 9-BIT WORDS0IDLE LINERX, TX DATA(SSFTD = 0)1234567START8STOP STARTx1 CLOCKx16 CLOCK(SCKP = 0)Figure 6-11 16 x Serial ClockMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 25Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)6.3.2.3.2SCCR Clock Out Divider (COD) Bit 12Figure 6-12 and Figure 6-35 show the clock divider circuit. The output divider is controlledby COD and the SCI mode.
If the SCI mode is synchronous, the output divider is fixed atdivide by 2; if the SCI mode is asynchronous, andFreescale Semiconductor, Inc...1. If COD equals zero and SCLK is an output (i.e., TCM and RCM=0), the SCIclock is divided by 16 before being output to the SCLK pin; thus, the SCLK output is a 1 × clock2. If COD equals one and SCLK is an output, the SCI clock is fed directly out tothe SCLK pin; thus, the SCLK output is a 16 × baud clockThe COD bit is cleared by hardware and software reset.6.3.2.3.3SCCR SCI Clock Prescaler (SCP) Bit 13The SCI SCP bit selects a divide by 1 (SCP=0) or divide by 8 (SCP=1) prescaler for the clockdivider. The output of the prescaler is further divided by 2 to form the SCI clock.
Hardware andsoftware reset clear SCP. Figure 6-12 and Figure 6-35 show the clock divider diagram.6.3.2.3.4SCCR Receive Clock Mode Source Bit (RCM) Bit 14RCM selects internal or external clock for the receiver (see Figure 6-35). RCM equals zeroselects the internal clock; RCM equals one selects the external clock from the SCLK pin.Hardware and software reset clear RCM.6.3.2.3.5SCCR Transmit Clock Source Bit (TCM) Bit 15The TCM bit selects internal or external clock for the transmitter (see Figure 6-35). TCMequals zero selects the internal clock; TCM equals one selects the external clock from theSCLK pin. Hardware and software reset clear TCM.6.3.2.4SCI Data RegistersThe SCI data registers are divided into two groups: receive and transmit.
There are tworeceive registers – a receive data register (SRX) and a serial-to-parallel receive shift register. There are also two transmit registers – a transmit data register (called either STX orSTXA) and a parallel-to-serial transmit shift register.6.3.2.4.1SCI Receive RegistersData words received on the RXD pin are shifted into the SCI receive shift register. Whenthe complete word has been received, the data portion of the word is transferred to thebyte-wide SRX.
This process converts the serial data to parallel data and provides double6 - 26PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)buffering. Double buffering provides flexibility and increased throughput since the programmer can save the previous word while the current word is being received.Freescale Semiconductor, Inc...The SRX can be read at three locations: X:$FFF4, X:$FFF5, and X:$FFF6 (see Figure6-13).
When location X:$FFF4 is read, the contents of the SRX are placed in the lowerbyte of the data bus and the remaining bits on the data bus are written as zeros. Similarly,when X:$FFF5 is read, the contents of SRX are placed in the middle byte of the bus, andwhen X:$FFF6 is read, the contents of SRX are placed in the high byte with the remainingbits zeroed. Mapping SRX as described allows three bytes to be efficiently packed intoTCMRCMTX ClockRX ClockSCLK PinMode00InternalInternalOutputSynchronous/Asynchronous01InternalExternalInputAsynchronous Only10ExternalInternalInputAsynchronous Only11ExternalExternalInputSynchronous/AsynchronousfoscDIVIDEBY 2DIVIDEBY 2PRESCALER:DIVIDE BY1 or 812-BIT COUNTERCD11 - CD0SCPINTERNAL CLOCKDIVIDEBY 16SCI CORE LOGICUSES DIVIDE BY 16 FORASYNCHRONOUSUSES DIVIDE BY 2 FORSYNCHRONOUSSTIRTIMERINTERRUPT(STMINT)CODIF ASYNCHRONOUSDIVIDE BY 1 OR 16IF SYNCHRONOUSDIVIDE BY 2foBPS = 64 x (7(SCP) + 1) x CD + 1)SCKPwhere:SCP = 0 or 1CD = 0 to $FFFSCKP = 0SCKP = 1+-TO SCLKFigure 6-12 SCI Baud Rate GeneratorMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 27Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...one 24-bit word by “OR”-ing three data bytes read from the three addresses.
The followingcode fragment requires that R0 initially points to X:$FFF4, register A is initially cleared,and R3 points to a data buffer. The only programming trick is using BCLR to test bit 1 ofthe packing pointer to see if it is pointing to X:$FFF6 and clearing bit 1 to point to X:$FFF4if it had been pointing to X:$FFF6. This procedure resets the packing pointer after receiving three bytes.FLAGMOVEBCLRX:(R0),X0#$1,R0ORMOVEJCSRTIMOVECLRRTIX0,A(R0)+FLAGA,(R3)+A;Copy received data to temporary register;Test for last byte;reset pointer if it is the last byte;Pack the data into register A;and increment the packing pointer;Jump to clean up routine if last byte;Else return until next byte is received;Move the packed data to memory;Prepare A for packing next three bytes;Return until the next byte is receivedThe length and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCI control register.
In the synchronous modes, the start bit, the eight databits with LSB first, the address/data indicator bit and/or the parity bit, and the stop bit arereceived in that order for SSFTD equals zero (see Figure 6-10 (a)). For SSFTD equalsone, the data bits are transmitted MSB first (see Figure 6-10(b)). The clock source is defined by the receive clock mode (RCM) select bit in the SCR. In the synchronous mode,the synchronization is provided by gating the clock. In either mode, when a complete wordhas been clocked in, the contents of the shift register can be transferred to the SRX andthe flags; RDRF, FE, PE, and OR are changed appropriately. Because the operation ofthe SCI receive shift register is transparent to the DSP, the contents of this register arenot directly accessible to the programmer.6.3.2.4.2SCI Transmit RegistersThe transmit data register is one byte-wide register mapped into four addresses:X:$FFF3, X:$FFF4, X:$FFF5, and X:$FFF6.
In the asynchronous mode, when data is tobe transmitted, X:$FFF4, X:$FFF5, and X:$FFF6 are used, and the register is called STX.When X:$FFF4 is written, the low byte on the data bus is transferred to the STX; whenX:$FFF5 is written, the middle byte is transferred to the STX; and when X:$FFF6 is written, the high byte is transferred to the STX. This structure (see Figure 6-9) makes it easyfor the programmer to unpack the bytes in a 24-bit word for transmission.
LocationX:$FFF3 should be written in the 11-bit asynchronous multidrop mode when the data is6 - 28PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...an address and it is desired that the ninth bit (the address bit) be set.
When X:$FFF3 iswritten, the transmit data register is called STXA, and data from the low byte on the databus is stored in STXA. The address data bit will be cleared in the 11-bit asynchronousmultidrop mode when any of X:$FFF4, X:$FFF5, or X:$FFF6 is written. When either STXor STXA is written, TDRE is cleared.The transfer from either STX or STXA to the transmit shift register occurs automatically,but not immediately, when the last bit from the previous word has been shifted out – i.e.,the transmit shift register is empty. Like the receiver, the transmitter is double buffered.However, there will be a two to four serial clock cycle delay between when the data istransferred from either STX or STXA to the transmit shift register and when the first bitappears on the TXD pin.
(A serial clock cycle is the time required to transmit one data bit).“A”X023“B”“C”16 158 70STXX:$FFF6MOVE X0, X:$FFF6; TRANSMIT CHARACTER “A”STXX:$FFF5MOVE X0, X:$FFF5; TRANSMIT CHARACTER “B”STXX:$FFF4MOVE X0, X:$FFF4; TRANSMIT CHARACTER “C”NOTE: STX is the same register decoded at three different addresses.(a) Unpacking23X:$FFF616 158 7SRXMOVE X0, X:$FFF6; RECEIVE CHARACTER “A”SRXX:$FFF5MOVE X0, X:$FFF5; RECEIVE CHARACTER “B”SRXX:$FFF4X00“A”“B”MOVE X0, X:$FFF4; RECEIVE CHARACTER “C”“C”NOTE: SRX is the same register decoded at three different addresses.(b) PackingFigure 6-13 Data Packing and UnpackingMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 29Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...The transmit shift register is not directly addressable, and a dedicated flag for this registerdoes not exist.
Because of this fact and the two to four cycle delay, two bytes cannot bewritten consecutively to STX or STXA without polling. The second byte will overwrite thefirst byte. The TDRE flag should always be polled prior to writing STX or STXA to preventoverruns unless transmit interrupts have been enabled. Either STX or STXA is usuallywritten as part of the interrupt service routine.
Of course, the interrupt will only be generated if TDRE equals one. The transmit shift register is indirectly visible via the TRNE bitin the SSR.In the synchronous modes, data is synchronized with the transmit clock, which may haveeither an internal or external source as defined by the TCM bit in the SCCR. The lengthand format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits inthe SCR. In the asynchronous modes, the start bit, the eight data bits (with the LSB firstif SSFTD=0 and the MSB first if SSFTD=1), the address/data indicator bit or parity bit, andthe stop bit are transmitted in that order (see Figure 6-10).The data to be transmitted can be written to any one of the three STX addresses. If SCKPequals one and SSHTD equals one, the SCI synchronous mode is equivalent to the SSIoperation in the 8-bit data on-demand mode.6.3.2.5Preamble, Break, and Data Transmission PriorityIt is possible that two or three transmission commands are set simultaneously:1.
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