Сигнальный МП Motorola DSP56002 (1086189), страница 31
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These registers are the Port Ccontrol register (PCC), Port C data direction register (PCDDR), and Port C data register(PCD) (see Figure 6-3).Freescale Semiconductor, Inc...ENABLED BYBITS INX:$FFE1PORTCPC0PC1PC2PC3PC4PC5PC6PC7PC8CC0CC1CC2CC3CC4CC5CC6CC7CC8DIRECTIONSELECTED BYX:$FFE3CD0CD1CD2CD3CD4CD5CD6CD7CD8INPUT/OUTPUTDATA REGISTERX:$FFE5PC0PC1PC2PC3PC4PC5PC6PC7PC8Figure 6-2 Port C GPIO ControlReset clears PCC and PCDDR to configure Port C as general-purpose I/O with all nine pinsas inputs. (External circuitry connected to these pins may need pullups until the pins areconfigured for operation.) Each Port C pin may be individually programmed as a general-purpose I/O pin or as a dedicated on-chip peripheral pin under software control.
Pin selection between general-purpose I/O and SCI or SSI is made by setting the appropriate PCCbit (memory location X:$FFE1) to zero for general-purpose I/O or to one for serial interface.The PCDDR (memory location X:$FFE3) programs each pin corresponding to a bit in the PCD(memory location X:$FFE5) as an input pin (if PCDDR=0) or as an output pin (if PCDDR=1).If a pin is configured as a GPIO input (as shown in Figure 6-4) and the processor readsthe PCD, the processor sees the logic level on the pin. If the processor writes to the PCD,the data is latched there, but does not appear on the pin because the buffer is in thehigh-impedance state.6-4PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.GENERAL-PURPOSE I/O (PORT C)23X:$FFE1000Freescale Semiconductor, Inc...CCx0000000000GPIO1Serial Interface0SSISTDSRDSCKSC2SC1SC0SCISCLKTXDRXDFunction000CC CC CC CC CC CC CC CC CC PORT C CONTROL876543210 REGISTER (PCC)230PORT C DATAX:$FFE3000000000000CDx000 CD CD CD CD CD CD CD CD CD DIRECTION876543010 REGISTER (PCDDR)Data Direction0Input1Output23X:$FFE52000000000000000PORT C DATAPD PD PD PD PD PD PD PD PDREGISTER (PCD)876543210NOTE: Hardware and software reset clears PCC and PCDDR.Figure 6-3 Port C GPIO RegistersIf a pin is configured as a GPIO output and the processor reads the PCD, the processorsees the contents of the PCD rather the logic level on the pin, which allows the PCD to beused as a general purpose 15-bit register.
If the processor writes to the PCD, the data islatched there and appears on the pin during the following instruction cycle (see 6.2.2).If a pin is configured as a serial interface (SCI or SSI) pin, the Port C GPIO registers canbe used to help in debugging the serial interface. If the PCDDR bit for a given pin iscleared (configured as an input), the PCD will show the logic level on the pin, regardlessof whether the serial interface function is using the pin as an input or an output. If the PCDDR is set (configured as an output) for a given serial interface pin, when the processorreads the PCD, it sees the contents of the PCD rather than the logic level on the pin —another case which allows the PCD to act as a general purpose register.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6-5Freescale Semiconductor, Inc.GENERAL-PURPOSE I/O (PORT C)Port ControlRegister BitData DirectionRegister Bit00Pin FunctionPort Input PinPINFreescale Semiconductor, Inc...PORT C DATA (PCD)REGISTER BIT(GPIOPOSITION)PORTREGISTERSDATA DIRECTIONREGISTER (PCDDR)PORT C CONTROL(PCC) REGISTER BIT(INPUTPOSITION)PORT INPUT DATA BITOUTPUT DATA BITPERIPHERALLOGICDATA DIRECTION BITINPUT DATA BITFigure 6-4 Port C I/O Pin Control Logic6.2.1Programming General Purpose I/OPort C and all the DSP56002 peripherals are memory mapped (see Figure 6-5).
The standard MOVE instruction transfers data between Port C and a register; as a result, performing a memory-to-memory data transfer takes two MOVE instructions and a register. TheMOVEP instruction is specifically designed for I/O data transfer as shown in Figure 6-6.Although the MOVEP instruction may take twice as long to execute as a MOVE instruction, only one MOVEP is required for a memory-to-memory data transfer, and MOVEPdoes not use a temporary register. Using the MOVEP instruction allows a fast interrupt tomove data to/from a peripheral to memory and execute one other instruction or to movethe data to an absolute address.
MOVEP is the only memory-to-memory move instruction;however, one of the operands must be in the top 64 locations of either X: or Y: memory.The bit-oriented instructions which use I/O short addressing (BCHG, BCLR, BSET, BTST,JCLR, JSCLR, JSET, and JSSET) can also be used to address individual bits for faster6-6PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.GENERAL-PURPOSE I/O (PORT C)::MOVEP #$0,X:$FFE1MOVEP #$01F0,X:$FFE3::MOVEP #data_out,X:$FFE5Freescale Semiconductor, Inc...MOVEP X:$FFE0,#data_in;Select Port C to be general-purpose I/O;Select pins PC0–PC3 to be inputs;and pins PC4–PC8 to be outputs;Put bits 4–8 of “data_out” on pins;PB4–PB8 bits 0–3 are ignored.;Put PB0–PB3 in bits 0–3 of “data_in”Figure 6-6 Write/Read Parallel Data with Port CI/O processing.The DSP does not have a hardware data strobe to strobe data out of the GPIO port. If a datastrobe is needed, it can be implemented using software to toggle one of the GPIO pins.Figure 6-7 shows the process of programming Port C as general-purpose I/O.
Normally, it is not good programming practice to activate a peripheral before programming it.However, reset activates the Port C general-purpose I/O as all inputs, and the alternative is to configure the port as an SCI and/or SSI, which may not be desirable. Inthis case, it is probably better to insure that Port C is initially configured for general-purpose I/O and then configure the data direction and data registers. It may be better in some situations to program the data direction or the data registers first to preventtwo devices from driving one signal. The order of steps 1, 2, and 3 in Figure 6-7 isoptional and can be changed as needed.6.2.2Port C General Purpose I/O TimingParallel data written to Port C is delayed by one instruction cycle.
For example, the following instruction:MOVEDATA9,X:PORTCDATA24,Y:EXTERN1. writes nine bits of data to the Port C register, but the output pins do not changeuntil the following instruction cycle2. writes 24 bits of data to the external Y memory, which appears on Port A during T2 and T3 of the current instructionAs a result, if it is necessary to synchronize the Port A and Port C outputs, two instructionsmust be used:MOVENOPMOTOROLADATA9,X:PORTCDATA24,Y:EXTERNPORT CFor More Information On This Product,Go to: www.freescale.com6-7Freescale Semiconductor, Inc.GENERAL-PURPOSE I/O (PORT C)Freescale Semiconductor, Inc...2316 15870X:$FFFFINTERRUPT PRIORITY REGISTER (IPR)X:$FFFEPORT A — BUS CONTROL REGISTER (BCR)X:$FFFDPLL CONTROL REGISTERX:$FFFCOnCE GDB REGISTERX:$FFFBRESERVEDX:$FFFARESERVEDX:$FFF9RESERVEDX:$FFF8RESERVEDX:$FFF7RESERVEDX:$FFF6SCI HI - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF5SCI MID - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF4SCI LOW - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF3SCI TRANSMIT DATA ADDRESS REGISTER (STXA)X:$FFF2SCI CONTROL REGISTER (SCCR)X:$FFF1SCI INTERFACE STATUS REGISTER (SSR)X:$FFF0SCI INTERFACE CONTROL REGISTER (SCR)X:$FFEFSSI RECIEVE/TRANSMIT DATA REGISTER (RX/TX)X:$FFEESSI STATUS/TIME SLOT REGISTER (SSISR/TSR)X:$FFEDSSI CONTROL REGISTER B (CRB)X:$FFECSSI CONTROL REGISTER A (CRA)X:$FFEBHOST RECEIVE/TRANSMIT REGISTER (HRX/HTX)X:$FFEARESERVEDX:$FFE9HOST STATUS REGISTER (HSR)6-8PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.GENERAL-PURPOSE I/O (PORT C)STEP 1.
SELECT EACH PIN TO BE GENERAL-PURPOSE I/O OR AN ON-CHIP PERIPHERAL PIN:CCx = 0GENERAL- PURPOSE I/OCCx = 1ON-CHIP PERIPHERAL8Freescale Semiconductor, Inc...X:$FFE10CC CC CC CC CC CC CC CC CC876543210PORT C CONTROL REGISTER (PCC)STEP 2. SET EACH GENERAL - PURPOSE I/O PIN (SELECTED ABOVE) AS INPUT OR OUTPUT:CDx = 0INPUT PINORCDx = 1OUTPUT PIN80CD CD CD CD CD CD CD CD CDX:$FFE3 876543210PORT C DATA DIRECTION REGISTER (PCDDR)STEP 3. READ/WRITE GENERAL - PURPOSE I/O PINS:PCx = OUTPUT DATA IF SELECTED FOR GENERAL - PURPOSE I/O AND OUTPUT IN STEPS 1 AND 2.ORPCx = INPUT DATA IF SELECTED FOR GENERAL - PURPOSE I/O AND INPUT IN STEPS 1 AND 2.80PC PC PC PC PC PC PC PC PCX:$FFE5 876543210PORT C DATA REGISTER (PCD)Figure 6-7 I/O Port C ConfigurationThe NOP can be replaced by any instruction that allows parallel moves.
Inserting one ormore “MOVE DATA15,X:PORTC DATA24,Y:EXTERN” instructions between the first andsecond instruction produces an external 33-bit write each instruction cycle with only oneinstruction cycle lost in setup time:MOVEMOVEMOVE::MOVENOPDATA9,X:PORTCDATA9,X:PORTCDATA9,X:PORTCDATA9,X:PORTCDATA24,Y:EXTERNDATA24,Y:EXTERNDATA24,Y:EXTERNDATA24,Y:EXTERNOne application of this technique is to create an extended address for Port A by concatenating the Port A address bits (instead of data bits) to the Port C general-purpose outputbits.
The Port C general-purpose I/O register would then work as a base address register,allowing the address space to be extended from 64K words (16 bits) to 33.5 million wordsMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6-9Freescale Semiconductor, Inc.GENERAL-PURPOSE I/O (PORT C)(16 bits+ 9 bits=25 bits).Freescale Semiconductor, Inc...Port C uses the DSP central processing unit (CPU) four-phase clock for its operation.Therefore, if wait states are inserted in the DSP CPU timing, they also affect Port C timing.As a result, Port A and Port C in the previous synchronization example will always staysynchronized, regardless of how many wait states are used.6 - 10PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)6.3SERIAL COMMUNICATION INTERFACE (SCI)The SCI provides a full-duplex port for serial communication to other DSPs, microprocessors, or peripherals such as modems.
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