Сигнальный МП Motorola DSP56002 (1086189), страница 27
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The jump-to-self instruction that follows is for test purposes only, it canbe replaced by any other code in normal operation.STEP 2 OF HOST PORT CONFIGURATION2. OPTION 5: SELECT DMA MODE FORINITIALIZE DSPINITIALIZE HI**BIT 7 = 124-BIT DMABIT 5 = 1BIT 6 = 0DSP TO HOSTOR16-BIT DMABIT 5 = 0BIT 6 = 1ORORHOST TO DSPDMA OFFBIT 5 = 1BIT 6 = 17$0INITENABLERECEIVE DATA FULL INTERRUPTBIT 0 = 1BIT 1 = 0ENABLETRANSMIT DATA EMPTY INTERRUPTBIT 0 = 0BIT 1 = 1OPTIONAL654HM1HM0HF13HF02*10TREQ RREQINTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)*Reserved; write as zero.**See Figure 5-23.Figure 5-21 (d) HI Initialization–Host Side, DMA ModeMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 43Freescale Semiconductor, Inc.HOST INTERFACE (HI)MODES7Freescale Semiconductor, Inc...HOST SETS INIT BITINIT0HM1HM0HF1HF00TREQ00Interrupt Mode (DMA Off)0124 Bit DMA Mode1016 Bit DMA Mode118 Bit DMA ModeINTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)RREQRESET CONDITIONINTERRUPT MODE (DMA OFF)DMA MODETREQRREQINIT Execution00INIT = 0; Address Counter = HM1, HM001INIT = 0; RXDF = 0; HTDE = 1;Address Counter = HM1, HM0TREQRREQ00INIT = 0; Address Counter = 001001INIT = 0; RXDF = 0; HTDE = 1;Address Counter = 00INIT = 0; TXDE = 1; HRDF = 0;Address Counter = HM1, HM011Undefined (Illegal)10INIT ExecutionINIT = 0; TXDE = 1; HRDF = 0;Address Counter = 00INIT is used by the HOST to force initialization of the HI hardware.The HI hardware automatically clears INIT when the command is executed.INIT is cleared by DSP RESET.Figure 5-22 Host Mode and INIT BitsThe receive routine in Figure 5-26 was implemented as a long interrupt (the instruction atthe interrupt vector location, which is not shown, is a JSR).
Since there is only one instruction, this could have been implemented as a fast interrupt. The MOVEP instruction movesdata from the HI to a buffer area in memory and increments the buffer pointer so that thenext word received will be put in the next sequential location.5.3.6.2.2Host to DSP – Command VectorThe host processor can cause three types of interrupts in the DSP (see Figure 5-27).These are host receive data (P:$0020), host transmit data (P:$0022), and host command(P:$0024 - P:$007E). The host command (HC) can be used to control the DSP by forcingit to execute any of 45 subroutines that can be used to run tests, transfer data, processdata, etc.
In addition, the HC can cause any of the other 19 interrupt routines in the DSPto be executed.The process to execute a HC (see Figure 5-28) is as follows:5 - 44PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLAHF3HF2TRDY TXDE RXDFDMA00HF1HF0HCPFor More Information On This Product,Go to: www.freescale.comPORT BINITHM00101HM10011HF00TREQ RREQ8 Bit DMA Mode16 Bit DMA Mode24 Bit DMA ModeInterrupt Mode (DMA Off)HF107000HF3Figure 5-23 Bits Used for Host-to-DSP TransferHRIE — HOST RECEIVE INTERRUPT ENABLEENABLES INTERRUPT AT P:$0020DSP INTERRUPT IS CAUSED BY HRDF = 11 = INTERRUPT P:$0020 ENABLED.0 = INTERRUPT P:$0020 DISABLED.INTERRUPT CONTROLREGISTER (ICR)X:$FFE8(READ/WRITE)TREQ — TRANSMIT REQUEST ENABLEUSED TO ENABLE INTERRUPTS THAT COME FROM TXDE TO THE HOSTVIA THE HREQ PIN.1 = TXDE INTERRUPTS PASS TO HREQ.0 = TXDE INTERRUPTS ARE MASKED.$07MODESHF2HCIE0HTDE HRDFHTIE0HRIEDMA —INDICATES THE HOST PROCESSOR HAS ENABLED THE DMA MODE1 = DMA ON.0 = HOST MODE.07TRDY — TRANSMITTER READY = TXDE • HRDF1 = BOTH THE TRANSMIT BYTE REGISTERS AND THE HOST RECEIVE DATAREGISTERS ARE EMPTY.0 = ONE OR BOTH REGISTERS ARE FULL.DMAINTERRUPT STATUSREGISTER (ISR)X:$FFE9(READ ONLY)HRDF — HOST RECEIVE DATA FULL1 = THE HOST RECEIVE REGISTER (HRX) CONTAINS DATA FROM THEHOST PROCESSOR.0 = HRX IS EMPTY.HREQ0DSP56002TXDE — TRANSMIT DATA REGISTER EMPTY1 = INDICATES THE TRANSMIT BYTE REGISTERS (TXH, TXM, TXL) ARE EMPTY.0 = CLEARED BY WRITING TO TXL; TXDE CAN BE USED TO ASSERT THEHREQ PIN.$27HOSTFreescale Semiconductor, Inc...HOST CONTROLREGISTER (HCR)(READ/WRITE)HOST STATUSREGISTER (HSR)(READ ONLY)Freescale Semiconductor, Inc.HOST INTERFACE (HI)5 - 455 - 460INIT7HF3HF2TRDYHM0HM1HF00TREQTRANSMIT REQUEST ENABLE00HF1TXDETRANSMIT DATA REGISTER EMPTYDMAHOST MAY POLL TXDE.HREQ11For More Information On This Product,Go to: www.freescale.comPORT BLAST WRITERREQ00TRANSFERX:$FFE90DMA700HF0HCPHIGH BYTEMIDDLE BYTE00HF3HF2HCIEHTIEHRIEHOST RECEIVE INTERRUPT ENABLE0P:$0020FAST INTERRUPTORLONG INTERRUPTHOST RECEIVE DATA VECTOR01LOW BYTE10.
IF HRDF = 1 AND INTERRUPTS ARE ENABLED, THEN EXCEPTIONPROCESSING BEGINS.X:$FFE879. THE TRANSFER SETS HRDF FOR THE DSP56002 TO POLL.X:$FFEB23HTDEHRDFHOST RECEIVE DATA FULLHF18. WHEN TXDE = 0 AND HRDF = 0, THEN TRANSFER OCCURS.INTERRUPT CONTROLREGISTER (ICR)INTERRUPT STATUSREGISTER (ISR)000VIEW FROM DSP560026. IF DSP560022 HAS OLD DATA IN HRX, THEN HRDF = 1.7. WHEN DSP56002 READS HRX, THEN HRDF = 0.Figure 5-24 Data Transfer from Host to DSPTRANSMIT BYTEREGISTERS (TBR)TXLTXM$6$7TXH$57WRITE TO TXL CLEARS TXDE IN ISR.HOST WRITES DATA TO TRANSMIT BYTE REGISTERS.HREQPIN0RXDFIF TREQ = 1, THEN HREQ PIN IS ASSERTED TO INTERRUPT HOST.027WHEN TXDE = 1, TDR IS EMPTY.VIEW FROM HOSTFreescale Semiconductor, Inc...HOST CONTROLREGISTER (HCR)HOST RECEIVEDATAREGISTER (HRX)HOST STATUSREGISTER (HSR)Freescale Semiconductor, Inc.HOST INTERFACE (HI)MOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)EXCEPTIONSTARTINGADDRESSPROGRAM MEMORY SPACEFreescale Semiconductor, Inc...EXCEPTION SOURCETWO WORDS PER VECTOR$0000HARDWARE RESET$0002STACK ERROR$0004TRACE$0006SWI (SOFTWARE INTERRUPT)$0008IRQA EXTERNAL HARDWARE INTERRUPT$000AIRQB EXTERNAL HARDWARE INTERRUPT$000CSSI RECEIVE DATA$000ESSI RECEIVE DATA WITH EXCEPTION STATUS$0010SSI TRANSMIT DATA$0012SSI TRANSMIT DATA WITH EXCEPTION STATUS$0014SCI RECEIVE DATA$0016SCI RECEIVE DATA WITH EXCEPTION STATUS$0018SCI TRANSMIT DATA$001ASCI IDLE LINE$001CSCI TIMER$001ERESERVED$0020HOST RECEIVE DATA$0022HOST TRANSMIT DATA$0024HOST COMMAND (DEFAULT)$0026AVAILABLE FOR HOST COMMAND$0028AVAILABLE FOR HOST COMMANDEXTERNAL INTERRUPTSINTERNALINTERRUPTSEXTERNALINTERRUPTSSYNCHRONOUSSERIALINTERFACEINTERNALINTERRUPTS•••$003CAVAILABLE FOR HOST COMMAND$003EILLEGAL INSTRUCTION$0040AVAILABLE FOR HOST COMMAND$0042AVAILABLE FOR HOST COMMAND$007EAVAILABLE FOR HOST COMMANDSERIALCOMMUNICATIONSINTERFACEHOSTINTERFACEINTERNALINTERRUPTS•••Figure 5-27 HI Exception Vector LocationsMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 475 - 48For More Information On This Product,Go to: www.freescale.comPORT B0HCHOST COMMAND15EXCEPTION VECTORADDRESS = HV x 2$12 — DEFAULTHOST VECTOR (HV)0$170HOST VECTOR (HV)HC — HOST COMMAND (STATUS)05COMMAND VECTORREGISTER (CVR)P:$007EP:$0024P:$0000X:$FFE8HF1HF0000HF3HF2FAST INTERRUPTORLONG INTERRUPTAVAILABLE FOR HOST COMMANDAVAILABLE FOR HOST COMMANDAVAILABLE FOR HOST COMMANDHOST COMMAND DEFAULT VECTOREXCEPTION VECTOR TABLEHCIEHOST COMMAND INTERRUPT ENABLE7Figure 5-28 Host Command00HCPHOST COMMAND PENDING04.
HOST COMMAND IS MASKED UNTIL HCIE = 1.DMA711HTIEHRIE0HTDE HRDF0VIEW FROM DSP560023. HCP IS SET UNTIL EXCEPTION IS ACKNOWLEDGED.COMMAND VECTOR X:$FFE9REGISTER (CVR)5. WHEN THE HOST COMMAND EXCEPTION IS ACKNOWLEDGED, THE HCBIT IS CLEARED BY THE HOST COMMAND LOGIC. HC CAN BE READ ASA STATUS BIT.$172. SET HC = 1.1. WRITE CVR WITH DESIRED HV.VIEW FROM HOSTFreescale Semiconductor, Inc...HOST CONTROLREGISTER (HCR)HOST STATUSREGISTER (HSR)Freescale Semiconductor, Inc.HOST INTERFACE (HI)1. The host processor writes the CVR with the desired HV (the HV is the DSP’sMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)2.3.4.Freescale Semiconductor, Inc...5.interrupt vector (IV) location divided by two - i.e.
if HV=$12, IV=$24).The HC is then set.The HCP bit in the HSR is set when HC is set.If the HCIE bit in the HCR has been set by the DSP, the HC exception processing will start. The HV is multiplied by 2 and the result is used by the DSPas the interrupt vector.When the HC exception is acknowledged, the HC bit (and therefore the HCPbit) is cleared by the HC logic. HC can be read by the host processor as a status bit to determine when the command is accepted.
Similarly, the HCP bit canbe read by the DSP CPU to determine if an HC is pending.To guarantee a stable interrupt vector, write HV only when HC is clear. The HC bit andHV can be written simultaneously. The host processor can clear the HC bit to cancel ahost command at any time before the DSP exception is accepted. Although the HV canbe programmed to any exception vector, it is not recommended that HV=0 (RESET) beused because it does not reset the DSP hardware.
DMA must be disabled to use the hostexception.5.3.6.2.3Host to DSP - Bootstrap Loading Using the HIThe circuit shown in Figure 5-29 will cause the DSP to boot through the HI on power up.During the bootstrap program, the DSP looks at the MODC, MODB, and MODA bits. If;****************************************; MAIN PROGRAM... receive data from host;****************************************ORGP:$40MOVE#0,R0MOVE#3,M0MOVEP#1,X:PBC;Turn on Host PortMOVEP#0,X:HCR;Turn off XMT and RCV interruptsMOVEP#$0C00,X:IPR ;Turn on host interruptMOVE#0,SR;Unmask interruptsJCLR#3,X:HSR,*;Wait for HF0 (from host) set to 1MOVEP#$1,X:HGR;Enable host receive interruptJMP*;Now wait for interruptFigure 5-25 Receive Data from Host–Main Program;************************************; Receive from Host Interrupt Routine;************************************RCVMOVEPX:HRX,X:(R0)+;Receive data.RTIENDFigure 5-26 Receive Data from Host Interrupt RoutineMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 49Freescale Semiconductor, Inc.HOST INTERFACE (HI)+5 VFreescale Semiconductor, Inc...DSP56002DRHENBRHACKWTMODA/IRQAFROM OPENCOLLECTORBUFFERLDSF32ASF32ADDRESSDECODEMODC/NMIA4-A23MC68000+5 V(12.5MHz)1KLS09FROMRESETFUNCTIONDTACKRESETMDB301*F32HR/W8H0-H73HA0-HA2MODB/IRQBFROM OPENCOLLECTORBUFFERF32R/WD0-D7A1-A3Notes: 1.
*This diode must be a Schottky diode.2. All resistors are 15KΩ unless noted otherwise.3. When in RESET, IRQA, IRQB and NMI mustbe deasserted by external peripherals.HOST7$0INITHM1HM0HF10HF00TREQ RREQINTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)SETTING HF0 TERMINATES BOOTSTRAP LOADING AND STARTSEXECUTION AT LOCATION P:$0000.SET HF0 FOR EARLY TERMINATIONHOST ADDRESSWRITTEN4 (DUMMY)567•••4 (DUMMY)567CONTENTS LOADEDTO INTERNAL P: RAM AT:P:$0000 HIGH BYTEP:$0000 MID BYTEP:$0000 LOW BYTE••••P:$01FF HIGH BYTEP:$01FF MID BYTEP:$01FF LOW BYTE• Because the DSP56002 is so fast, host handshaking is generally not required.Figure 5-29 Bootstrap Using the HI5 - 50PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.Freescale Semiconductor, Inc...HOST INTERFACE (HI)the bits are set at 101 respectively, the DSP will load from the HI.
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