Сигнальный МП Motorola DSP56002 (1086189), страница 23
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HF0 maybe set or cleared by the host processor and cannot be changed by the DSP. HF0 is visible in the HSR on the DSP CPU side of the HI (see Figure 5-10). Hardware, software,individual, and STOP resets clear HF0.5.3.3.2.5ICR Host Flag 1 (HF1) Bit 4The HF1 bit is used as a general-purpose flag for host-to-DSP communication. HF1 maybe set or cleared by the host processor and cannot be changed by the DSP. Hardware,software, individual, and STOP resets clear HF1.5.3.3.2.6ICR Host Mode Control (HM1 and HM0 bits) Bits 5 and 6The HM0 and HM1 bits select the transfer mode of the HI (see Table 5-3). HM1 and HM0enable the DMA mode of operation or interrupt (non-DMA) mode of operation.When both HM1 and HM0 are cleared, the DMA mode is disabled, and the TREQ andRREQ control bits are used for host processor interrupt control via the external HREQ out-MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 23Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...Table 5-3 Host Mode Bit DefinitionHM1HM0Mode00Interrupt Mode (DMA Off)01DMA Mode (24 Bit)10DMA Mode (16 Bit)11DMA Mode (8 Bit)put pin.
Also, in the non-DMA mode, the HACK input pin is used for the MC68000 Familyvectored interrupt acknowledge input.When HM1 or HM0 are set, the DMA mode is enabled, and the HREQ pin is used torequest DMA transfers. When the DMA mode is enabled, the TREQ and RREQ bits selectthe direction of DMA transfers. The HACK input pin is used as a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected registerare enabled onto the host data bus when HACK is asserted. If the DMA direction is fromhost to DSP, the selected register is written from the host data bus when HACK is asserted.The size of the DMA word to be transferred is determined by the DMA control bits, HM0and HM1. The HI register selected during a DMA transfer is determined by a 2-bit addresscounter, which is preloaded with the value in HM1 and HM0.
The address counter substitutes for the HA1 and HA0 bits of the HI during a DMA transfer. The host address bit (HA2)is forced to one during each DMA transfer. The address counter can be initialized with theINIT bit feature. After each DMA transfer on the host data bus, the address counter isincremented to the next register. When the address counter reaches the highest register(RXL or TXL), the address counter is not incremented but is loaded with the value in HM1and HM0. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 pins. For 16- or24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate – i.e., for every two or three host processor data transfersof one byte each, there is only one 24-bit DSP CPU interrupt.Hardware, software, individual, and STOP resets clear HM1 and HM0.5.3.3.2.7ICR Initialize Bit (INIT) Bit 7The INIT bit is used by the host processor to force initialization of the HI hardware.
Initialization consists of configuring the HI transmit and receive control bits and loading HM1and HM0 into the internal DMA address counter. Loading HM1 and HM0 into the DMAaddress counter causes the HI to begin transferring data on a word boundary rather than5 - 24PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...transferring only part of the first data word.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 25Freescale Semiconductor, Inc.HOST INTERFACE (HI)Table 5-4 HREQ Pin DefinitionTREQRREQTransferDirectionInitializedAfter INIT ExecutionFreescale Semiconductor, Inc...Interrupt Mode (HM1 = 0, HM0 = 0) INIT Execution00INIT = 0; Address Counter = 00None01INIT = 0; RXDF = 0; HTDE = 1; AddressCounter = 00DSP to Host10INIT = 0; TXDE = 1; HRDF = 0; AddressCounter = 00Host to DSP11INIT = 0; RXDF = 0; HTDE = 1; TXDE =1; HRDF = 0; Address Counter = 00Host to/from DSPDMA Mode (HM1 or HM0 = 1) INIT Execution00INIT = 0; Address Counter = HM1, HM0None01INIT = 0; RXDF = 0; HTDE = 1; AddressCounter = HM1, HM0DSP to Host10INIT = 0; TXDE = 1; HRDF = 0; AddressCounter = HM1, HM0Host to DSP11Undefined (Illegal)UndefinedThere are two methods of initialization: 1) allowing the DMA address counter to be automatically set after transferring a word, and 2) setting the INIT bit, which sets the DMAaddress counter.
Using the INIT bit to initialize the HI hardware may or may not be necessary, depending on the software design of the interface.The type of initialization done when the INIT bit is set depends on the state of TREQ andRREQ in the HI. The INIT command, which is local to the HI, is designed to convenientlyconfigure the HI into the desired data transfer mode. The commands are described in thefollowing paragraphs and in Table 5-4. The host sets the INIT bit, which causes the HI hardware to execute the INIT command.
The interface hardware clears the INIT bit when thecommand has been executed. Hardware, software, individual, and STOP resets clear INIT.INIT execution always loads the DMA address counter and clears the channel accordingto TREQ and RREQ. INIT execution is not affected by HM1 and HM0.The internal DMA counter is incremented with each DMA transfer (each HACK pulse) untilit reaches the last data register (RXL or TXL). When the DMA transfer is completed, thecounter is loaded with the value of the HM1 and HM0 bits.
When changing the size of the5 - 26PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...DMA word (changing HM0 and HM1 in the ICR), the DMA counter is not automaticallyupdated, and, as a result, the DMA counter will point to the wrong data register immediately after HM1 and HM0 are changed. The INIT function must be used to preset theinternal DMA counter correctly. Always set INIT after changing HM0 and HM1.
However,the DMA counter can not be initialized in the middle of a DMA transfer. Even though theINIT bit is set, the internal DMA controller will wait until after completing the data transferin progress before executing the initialization.5.3.3.3Command Vector Register (CVR)The host processor uses the CVR to cause the DSP to execute a vectored interrupt.
Thehost command feature is independent of the data transfer mechanisms in the HI. It canbe used to cause any of the 64 possible interrupt routines in the DSP CPU to be executed. The command vector register is shown in Figure 5-14.5.3.3.3.1CVR Host Vector (HV) Bits 0–5The six HV bits select the host command exception address to be used by the host command exception logic. When the host command exception is recognized by the DSPinterrupt control logic, the starting address of the exception taken is 2×HV. The host canwrite HC and HV in the same write cycle, if desired.76543210HC*HV5HV4HV3HV2HV1HV0HOST VECTORRESERVEDHOST COMMANDFigure 5-14 Command Vector RegisterThe host processor can select any of the 64 possible exception routine starting addressesin the DSP by writing the exception routine starting address divided by 2 into HV.
Thismeans that the host processor can force any of the existing exception handlers (SSI, SCI,IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused startingaddresses provided they have been preprogrammed in the DSP. HV is set to $12 (vectorlocation $0024) by hardware, software, individual, and STOP resets. Vector location$0024 is the first of 45 special host command vectors.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 27Freescale Semiconductor, Inc.HOST INTERFACE (HI)CAUTIONThe HV should not be used with a value of zero because the reset locationis normally programmed with a JMP instruction.
Doing so will cause an improper fast interrupt.Freescale Semiconductor, Inc...5.3.3.3.2CVR Reserved Bit (Bit 6)Reserved bit which is unused and read by the host processor as zero.5.3.3.3.3CVR Host Command Bit (HC) Bit 7The HC bit is used by the host processor to handshake the execution of host commandexceptions. Normally, the host processor sets HC=1 to request the host commandexception from the DSP. When the host command exception is acknowledged by theDSP, the HC bit is cleared by the HI hardware. The host processor can read the state ofHC to determine when the host command has been accepted. The host processor mayelect to clear the HC bit, canceling the host command exception request at any timebefore it is accepted by the DSP CPU.CAUTIONThe command exception might be recognized by the DSP and executed before it can be canceled by the host, even if the host clears the HC bit.Setting HC causes host command pending (HCP) to be set in the HSR.
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