Сигнальный МП Motorola DSP56002 (1086189), страница 25
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If HR/Wis high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the hostprocessor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. HR/W is stable when HEN is asserted. It can be programmed as ageneral-purpose I/O pin (PB11) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset.5.3.4.4Host Enable (HEN)This input enables a data transfer on the host data bus. When HEN is asserted and HR/Wis high, H0–H7 become outputs and the host processor may read DSP56002 data.
WhenHEN is asserted and HR/W is low, H0–H7 become inputs. When HEN is deasserted, hostdata is latched inside the DSP. Normally, a chip select signal derived from host addressdecoding and an enable clock are used to generate HEN. HEN can be programmed as ageneral-purpose I/O pin (PB12) when the host interface is not being used, and is configured as a GPIO input pin during hardware reset.5.3.4.5Host Request (HREQ)This open-drain output signal is used by the DSP56002 HI to request service from the hostprocessor, DMA controller, or a simple external controller.
HREQ may be connected to aninterrupt request pin of a host processor, a transfer request of a DMA controller or a control input of external circuitry. HREQ is asserted when an enabled request occurs in thehost interface. HREQ is deasserted when the enabled request is cleared or masked, DMAHACK is asserted, or the DSP is reset. HREQ may be programmed as a general purposeI/O pin (not open-drain) called PB13 when the HI is not being used.5.3.4.6Host Acknowledge (HACK)The Port B Control register allows the user to program this input independently of theother Host Interface pins. When the port is defined for general purpose I/O, this input actsTable 5-6 Port B Pin DefinitionsMOTOROLABC0BC1Function00Parallel I/O (Reset Condition)01Host Interface10Host Interface (HACK is defined as general purpose I/O)11ReservedPORT BFor More Information On This Product,Go to: www.freescale.com5 - 33Freescale Semiconductor, Inc.HOST INTERFACE (HI)as a general purpose I/O pin called PB14.
When the port is defined as the host interface,the user may manipulate the Port B Control register to program this input as either PB14,or as the HACK pin. The table below shows the Port B Control register bit configurations.HACK may act as a data strobe for HI DMA data transfers (See Figure 5-18). Or, if HACKis used as an MC68000 host interrupt acknowledge, it enables the HI interrupt vector register (IVR) on the host data bus H0-H7 if HREQ is asserted (See Figure 5-16). In this case,all other HI control pins are ignored and the state of the HI is not affected.Freescale Semiconductor, Inc...Note: HACK should always be pulled high when it is not in use.5.3.5Servicing the Host InterfaceThe HI can be serviced by using one of the following protocols:1.
Polling2. Interrupts, which can be eithera. non-DMAb. DMAFrom the host processor viewpoint, the service consists of making a data transfer sincethis is the only way to reset the appropriate status bits.DSP560023HA0 - HA2HA0 - HA2HR/WHR/WHENHEN8H0 - H7H0 - H7+5 VWRITEDATALATCHEDIN HIREADHREQ+5 VHACKFigure 5-15 Host Processor Transfer Timing5 - 34PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)5.3.5.1HI Host Processor Data TransferThe HI looks like static RAM to the host processor. Accordingly, in order to transfer datawith the HI, the host processor:Freescale Semiconductor, Inc...1. asserts the HI address (HA0, HA1, HA2) to select the register to be read or written2. asserts HR/W to select the direction of the data transfer3. strobes the data transfer using HEN.
When data is being written to the HI by thehost processor, the positive-going edge of HEN latches the data in the HI registerselected. When data is being read by the host processor, the negative-going edgeof HEN strobes the data onto the data bus H0-H7Figure 5-15 illustrates this process. The specified timing relationships are given in theDSP56002 Technical Data Sheet.5.3.5.2HI Interrupts Host Request (HREQ)The host processor interrupts are external and use the HREQ pin. HREQ is normally connected to the host processor maskable interrupt (IPL0, IPL1 or IPL2 in Figure 5-16) input.70$3MC68000INTERRUPT VECTOR NUMBERINTERRUPT VECTOR REGISTER (IVR)(READ/WRITE)1.
THE DSP56002 ASERTS HREQ TO INTERRUPT THE HOST PROCESSOR. +5 VIPL2IPL1IPL0DSP560021KHREQ2. THE HOST PROCESSOR ASSERTS HACK WITH ITS INTERRUPTACKNOWLEDGE CYCLE.HACKIACKA1 - A31FC0 - FC2IACKLOGICAS$0F3. WHEN HREQ AND HACK ARE SIMULTANEOUSLY ASSERTED, THECONTENTS OF THE IVR ARE PLACED ON THE HOST DATA BUS.INTERRUPTVECTORREGISTER(IVR)H0 - H7D0 - D7Figure 5-16 Interrupt Vector Register Read TimingThe host processor acknowledges host interrupts by executing an interrupt service rou-MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 35Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...tine.
The most significant bit (HREQ) of the ISR may be tested by the host processor todetermine if the DSP is the interrupting device and the two least significant bits (RXDFand TXDE) may be tested to determine the interrupt source (see Figure 5-17). The hostprocessor interrupt service routine must read or write the appropriate HI register to clearthe interrupt. HREQ is deasserted when1) the enabled request is cleared or masked, 2)DMA HACK is asserted, or 3) the DSP is reset.5.3.5.3PollingIn the polling mode of operation, the HREQ pin is not connected to the host processor andHACK must be deasserted to insure DMA data or IVR data is not being output on H0-H7when other registers are being polled.The host processor first performs a data read transfer to read the ISR (see Figure 5-17)to determine, whether:1.
RXDF=1, signifying the receive data register is full and therefore a data readshould be performed2. TXDE=1, signifying the transmit data register is empty so that a data write canbe performed3. TRDY=1, signifying the transmit data register is empty and that the receivedata register on the DSP CPU side is also empty so that the data written bythe host processor will be transferred directly to the DSP side4. HF2 • HF3 ≠ 0, signifying an application-specific state within the DSP CPUhas been reached, which requires action on the part of the host processor5.
DMA=1, signifying the HI is currently being used for DMA transfers. If DMAtransfers are possible in the system, deactivate HACK prior to reading the ISRso both DMA data and the contents of ISR are not simultaneously output onH0- H76. If HREQ=1, the HREQ pin has been asserted, and one of the previous fiveconditions existsGenerally, after the appropriate data transfer has been made, the corresponding statusbit will toggle.If the host processor has issued a command to the DSP by writing the CVR and settingthe HC bit, it can read the HC bit in the CVR to determine when the command has beenaccepted by the interrupt controller in the DSP’s central processing module.
When thecommand has been accepted for execution, the interrupt controller will reset the HC bit.5 - 36PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)STATUS7$20HREQDMA0HF3HF2TRDYTXDEISRRXDFEXCEPTION SOURCEHREQ ASSERTEDFreescale Semiconductor, Inc...HREQ7$30INITHM1HM0HF1HF00TREQRREQICRMASKFigure 5-17 HI Interrupt Structure5.3.5.4Servicing Non-DMA InterruptsWhen HM0=HM1=0 (non-DMA) and HREQ is connected to the host processor interruptinput, the HI can request service from the host processor by asserting HREQ. In the nonDMA mode, HREQ will be asserted when TXDE=1 and/or RXDF=1 and the corresponding mask bit (TREQ or RREQ, respectively) is set. This is depicted in Figure 5-17.Generally, servicing the interrupt starts with reading the ISR, as described in the previoussection on polling, to determine which DSP has generated the interrupt and why.
Whenmultiple DSPs occur in a system, the HREQ bit in the ISR will normally be read first todetermine the interrupting device. The host processor interrupt service routine must reador write the appropriate HI register to clear the interrupt. HREQ is deasserted when theenabled request is cleared or masked.In the case where the host processor is a member of the MC680XX Family, servicing theinterrupt will start by asserting HREQ to interrupt the processor (see Figure 5-17). Thehost processor then acknowledges the interrupt by asserting HACK. While HREQ andHACK are simultaneously asserted, the contents of the IVR are placed on the host databus. This vector will tell the host processor which routine to use to service the HREQinterrupt.The HREQ pin is an open-drain output pin so that it can be wire-ORed with the HREQ pinsfrom other DSP56002 processors in the system. When the DSP56002 generates an interrupt request, the host processor can poll the HREQ bit in each of the ISRs to determinewhich device generated the interrupt.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 37Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...5.3.5.5Servicing DMA InterruptsWhen HM0≠0 and/or HM1≠0, HREQ will be asserted to request a DMA transfer.
Generally the HREQ pin will be connected to the REQ input of a DMA controller. The HA0-2,HEN, and HR/W pins are not used during DMA transfers; DMA transfers only use theHREQ and HACK pins after the DMA channel has been initialized. HACK is used to strobethe data transfer as shown in Figure 5-18 where an MC68440 is used as the DMA controller. DMA transfers to and from the HI are considered in more detail in Section 5.3.6 HIApplication Examples.5.3.6HI Application ExamplesThe following paragraphs describe examples of initializing the HI, transferring data withthe HI, bootstrapping via the HI, and performing DMA transfers through the HI.5.3.6.1HI InitializationInitializing the HI takes two steps (see Figure 5-19).
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