Сигнальный МП Motorola DSP56002 (1086189), страница 21
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It occupies the low-orderbyte of the internal data bus; the high-order portion is zero filled. Any reserved bits areread as zeros and should be programmed as zeros for future compatibility. (The bit manipulation instructions are useful for accessing the individual bits in the HCR.) The contentsof the HCR are cleared on hardware or software reset. The control bits are described inthe following paragraphs.5.3.2.1.1HCR Host Receive Interrupt Enable (HRIE) Bit 0The HRIE bit is used to enable a DSP interrupt when the host receive data full (HRDF)status bit in the host status register (HSR) is set. When HRIE is cleared, HRDF interruptsare disabled. When HRIE is set, a host receive data interrupt request will occur if HRDFis also set. Hardware and software resets clear HRIE.5.3.2.1.2HCR Host Transmit Interrupt Enable (HTIE) Bit 1The HTIE bit is used to enable a DSP interrupt when the host transmit data empty(HTDE) status bit in the HSR is set.
When HTIE is cleared, HTDE interrupts are disabled.When HTIE is set, a host transmit data interrupt request will occur if HTDE is also set.Hardware and software resets clear the HTIE.5.3.2.1.3HCR Host Command Interrupt Enable (HCIE) Bit 2The HCIE bit is used to enable a vectored DSP interrupt when the host command pending (HCP) status bit in the HSR is set. When HCIE is cleared, HCP interrupts are disabled. When HCIE is set, a host command interrupt request will occur if HCP is also set.The starting address of this interrupt is determined by the host vector (HV).
Hardwareand software resets clear the HCIE.5.3.2.1.4HCR Host Flag 2 (HF2) Bit 3The HF2 bit is used as a general-purpose flag for DSP-to-host communication. HF2 maybe set or cleared by the DSP. HF2 is visible in the interrupt status register (ISR) on thehost processor side (see Figure 5-10). Hardware and software resets clear HF2.5 - 14PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...5.3.2.1.5HCR Host Flag 3 (HF3) Bit 4The HF3 bit is used as a general-purpose flag for DSP-to-host communication. HF3 maybe set or cleared by the DSP.
HF3 is visible in the ISR on the host processor side (seeFigure 5-10). Hardware and software resets clear HF3.Note: There are four host flags: two used by the host to signal the DSP (HF0 and HF1)and two used by the DSP to signal the host processor (HF2 and HF3). They aregeneral purpose flags and are not designated for any specific purpose. The hostflags do not cause interrupts; they must be polled to see if they have changed.These flags can be used individually or as encoded pairs. See Section 5.3.2.7Host Port Usage Considerations – DSP Side for additional information.
An example of the usage of host flags is the bootstrap loader, which is listed in theDSP56001 Technical Data Sheet. Host flags are used to tell the bootstrap programwhether or not to terminate early.5.3.2.1.6HCR Reserved Control (Bits 5, 6, and 7)These unused bits are reserved for future expansion and should be written with zeros forupward compatibility.5.3.2.2Host Status Register (HSR)The HSR is an 8-bit read-only status register used by the DSP to interrogate status andflags of the HI.
It can not be directly accessed by the host processor. When the HSR isread to the internal data bus, the register contents occupy the low-order byte of the databus; the high-order portion is zero filled. The status bits are described in the followingparagraphs.5.3.2.2.1HSR Host Receive Data Full (HRDF) Bit 0The HRDF bit indicates that the host receive data register (HRX) contains data from thehost processor.
HRDF is set when data is transferred from the TXH:TXM:TXL registersto the HRX register. HRDF is cleared when HRX is read by the DSP. HRDF can also becleared by the host processor using the initialize function. Hardware, software, individual,and STOP resets clear HRDF.5.3.2.2.2HSR Host Transmit Data Empty (HTDE) Bit 1The HTDE bit indicates that the host transmit data register (HTX) is empty and can be writtenby the DSP. HTDE is set when the HTX register is transferred to the RXH:RXM:RXL registers.
HTDE is cleared when HTX is written by the DSP. HTDE can also be set by the hostprocessor using the initialize function. Hardware, software, individual, and STOP sets HTDE.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 15Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...5.3.2.2.3HSR Host Command Pending (HCP) Bit 2The HCP bit indicates that the host has set the HC bit and that a host command interruptis pending.
The HCP bit reflects the status of the HC bit in the command vector register(CVR). HC and HCP are cleared by the DSP exception hardware when the exception istaken. The host can clear HC, which also clears HCP. Hardware, software, individual,and STOP resets clear HCP.5.3.2.2.4HSR Host Flag 0 (HF0) Bit 3The HF0 bit in the HSR indicates the state of host flag 0 in the ICR on the host processorside. HF0 can only be changed by the host processor (see Figure 5-10).
Hardware, software, individual, and STOP resets clear HF0.5.3.2.2.5HSR Host Flag 1 (HF1) Bit 4The HF1 bit in the HSR indicates the state of host flag 1 in the ICR on the host processorside. HF1 can only be changed by the host processor (see Figure 5-10). Hardware, software, individual, and STOP resets clear HF1.HOST TO DSP56002 STATUS FLAGS7HOST$00INITHM1HM0HF1HF00TREQ7DSP56002X:$FFE9INTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)RREQ0DMA00HF1HF0HCPHTDEHOST STATUS REGISTER (HSR)(READ ONLY)HRDFDSP56002 TO HOST STATUS FLAGS7HOST$20HREQDMA0HF3HF2TRDYTXDE7DSP56002X:$FFE8INTERRUPT STATUS REGISTER (ISR)(READ ONLY)RXDF0000HF3HF2HCIEHTIEHRIEHOST CONTROL REGISTER (HCR)(READ/WRITE)Figure 5-10 Host Flag Operation5 - 16PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...5.3.2.2.6HSR Reserved Status (Bits 5 and 6)These status bits are reserved for future expansion and read as zero during DSPread operations.5.3.2.2.7HSR DMA Status (DMA) Bit 7The DMA bit indicates that the host processor has enabled the DMA mode of the HI bysetting HM1 or HM0 to one.
When the DMA bit is zero, it indicates that the DMA mode isdisabled by the HM0 and HM1 bits in the ICR and that no DMA operations are pending.When the DMA bit is set, the DMA mode has been enabled if one or more of the hostmode bits have been set to one. The channel not in use can be used for polled or interrupt operation by the DSP. Hardware, software, individual, and STOP resets clear theDMA bit.5.3.2.3Host Receive Data Register (HRX)The HRX register is used for host-to-DSP data transfers.
The HRX register is viewed asa 24-bit read-only register by the DSP CPU. The HRX register is loaded with 24-bit datafrom the transmit data registers (TXH:TXM:TXL) on the host processor side when boththe transmit data register empty TXDE (host processor side) and DSP host receive datafull (HRDF) bits are cleared. This transfer operation sets TXDE and HRDF. The HRX register contains valid data when the HRDF bit is set. Reading HRX clears HRDF. The DSPmay program the HRIE bit to cause a host receive data interrupt when HRDF is set.Resets do not affect HRX.5.3.2.4Host Transmit Data Register (HTX)The HTX register is used for DSP-to-host data transfers.
The HTX register is viewed as a24-bit write-only register by the DSP CPU. Writing the HTX register clears HTDE. TheDSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set.The HTX register is transferred as 24-bit data to the receive byte registers(RXH:RXM:RXL) if both the HTDE bit (DSP CPU side) and receive data full (RXDF) statusbits (host processor side) are cleared. This transfer operation sets RXDF and HTDE.
Datashould not be written to the HTX until HTDE is set to prevent the previous data from beingoverwritten. Resets do not affect HTX.5.3.2.5Register Contents After ResetTable 5-1 shows the results of four reset types on bits in each of the HI registers seen bythe DSP CPU. The hardware reset (HW) is caused by the RESET signal; the softwarereset (SW) is caused by executing the RESET instruction; the individual reset (IR) iscaused by clearing PBC register bits 0 and 1, and the stop reset (ST) is caused by executing the STOP instruction.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 17Freescale Semiconductor, Inc.HOST INTERFACE (HI)Table 5-1 Host Registers afterReset–DSP CPU SideReset TypeRegisterNameRegisterDataHWResetSWResetIRResetSTResetHF(3 - 2)00——HCIE00——HTIE00——HRIE00——DMA0000HF(1 - 0)0000HCP0000HTDE1111HRDF0000HRXHRX (23 - 0)————HTXHTX (23 - 0)————Freescale Semiconductor, Inc...HCRHSR5.3.2.6Host Interface DSP CPU InterruptsThe HI may request interrupt service from either the DSP or the host processor.
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