Сигнальный МП Motorola DSP56002 (1086189), страница 19
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.2GENERAL PURPOSE I/O CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . 5-45.3HOST INTERFACE (HI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10Freescale Semiconductor, Inc...5.15-2PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.INTRODUCTIONFreescale Semiconductor, Inc...5.1INTRODUCTIONPort B is a dual-purpose I/O port. It performs as 15 general-purpose I/O (GPIO) pins,each configurable as output or input, to be used for device control.
Or, it can perform asan 8-bit bidirectional host interface (HI) (see Figure 5-1), where it provides a convenientconnection to another processor. This section describes both configurations, includingexamples of how to configure and use the port.DEFAULTFUNCTIONALTERNATEFUNCTION16EXTERNAL ADDRESSSWITCHA0 - A15—D0 - D23—24EXTERNAL DATASWITCHPSDSX/YRDWRBNBRBGWTBSPORTAI/0(47)BUSCONTROL8HOST/DMAPARALLELINTERFACEPORTBI/0(15)SCIINTERFACEPORTCI/0(9)SSIINTERFACE——————————8PB0 - PB7PB8PB9PB10PB11PB12PB13PB14H0 - H7HA0HA1HA2HR/WHENHREQHACK or PB14PC0RXDPC1TXDPC2SCLKPC3SC0PC4SC1PC5SC2PC6SCKPC7SRDPC8STDFigure 5-1 Port B InterfaceMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5-3Freescale Semiconductor, Inc.GENERAL PURPOSE I/O CONFIGURATION5.2GENERAL PURPOSE I/O CONFIGURATIONWhen it is configured as general-purpose I/O, Port B acts as three memory-mapped registers (see Figure 5-2) that control 15 I/O pins (see Figure 5-3).
They are the Port B controlregister (PBC), Port B data direction register (PBDDR), and Port B data register (PBD).Freescale Semiconductor, Inc...The software and hardware resets clear the PBC and PBDDR, which configures Port Bas general-purpose I/O, with all 15 pins as inputs. (External circuitry connected to thesepins may need pullups until the pins are configured for operation.)To select between general purpose I/O and the HI, set PBC bits 0 and 1 as shown in Figure 5-2. Use the PBDDR to determine whether the corresponding bit in the PBD shall bean input pin (bit is set to zero) or an output pin (bit is set to one).If a pin is configured as a GPIO input (as shown in Figure 5-4) and the processor readsthe PBD, the processor sees the logic level on the pin. If the processor writes to the PBD,the data is latched there, but does not appear on the pin because the buffer is in the highimpedance state.23X:$FFE0000000000000000000000BC1BC000Parallel I/O (Reset Condition)01Host Interface10Host Interface (with HACK pin as GPIO)11Reserved00Function23X:$FFE20000000014131211109876543210Data Direction0Input (Reset Condition)1Output230PORT B DATADIRECTIONREGISTER (PBDDR)0 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD0BDxX:$FFE4PORT B CONTROLREGISTER (PBC)BC BC10000000000PB PB PB PB PB PB PB PB PB PB PB PB PB PB PB14 13 12 11 10 9876543210PORT B DATAREGISTER (PBD)Figure 5-2 Parallel Port B Registers5-4PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.GENERAL PURPOSE I/O CONFIGURATIONENABLED BYBITS INX:$FFE0PORTFreescale Semiconductor, Inc...BPB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14DIRECTIONSELECTED BYX:$FFE2INPUT/OUTPUTDATAX:$FFE4BD0BD1BD2BD3BD4BD5BD6BD7BD8BD9BD10BD11BD12BD13BD14PB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1BC0/BC1Figure 5-3 Parallel Port B PinoutIf a pin is configured as a GPIO output and the processor reads the PBD, the processorsees the contents of the PBD rather the logic level on the pin, which allows the PBD to beused as a general purpose 15-bit register.
If the processor writes to the PBD, the data islatched there and appears on the pin during the following instruction cycle (see Section5.2.2 Port B General Purpose I/O Timing).If a pin is configured as a host pin, the Port B GPIO registers can be used to help indebugging the HI. If the PBDDR bit for a given pin is cleared (configured as an input), thePBD will show the logic level on the pin, regardless of whether the HI function is using thepin as an input or an output.If the PBDDR is set (configured as an output) for a given pin that is configured as a hostpin, when the processor reads the PBD, it sees the contents of the PBD rather than thelogic level on the pin - another case which allows the PBD to act as a general purposeregister.Note: The external host processor should be carefully synchronized to the DSP56002 toassure that the DSP and the external host will properly read status bits transmittedbetween them.
There is more discussion of such port usage considerations in sections Section 5.3.2.7 Host Port Usage Considerations – DSP Side and Section5.3.6.5 Host Port Usage Considerations – Host Side.5.2.1Programming General Purpose I/OPort B is a memory-mapped peripheral as are all of the DSP56002 peripherals (seeFigure 5-5). The standard MOVE instruction transfers data between Port B and a register; as a result, MOVE takes two instructions to perform a memory-to-memory dataMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5-5Freescale Semiconductor, Inc.GENERAL PURPOSE I/O CONFIGURATIONPort ControlRegister BitData DirectionRegister Bit00Pin FunctionPort Input PinPINFreescale Semiconductor, Inc...PORT B DATA (PBD)REGISTER BIT(GPIOPOSITION)PORTREGISTERSDATA DIRECTIONREGISTER (PBDDR) BITPORT B CONTROLREGISTER (PBC) BIT(INPUTPOSITION)PORT INPUT DATA BITHI OUTPUT DATA BITPERIPHERALLOGICHI DATA DIRECTION BITHI INPUT DATA BITFigure 5-4 Port B I/O Pin Control Logictransfer and uses a temporary holding register.
The MOVEP instruction is specificallydesigned for I/O data transfer as shown in Figure 5-6. Although the MOVEP instruction may take twice as long to execute as a MOVE instruction, only one MOVEP isrequired for a memory-to-memory data transfer, and MOVEP does not use a temporary register.
Using the MOVEP instruction allows a fast interrupt to move data to/froma peripheral to memory and execute one other instruction or move the data to an absolute address. MOVEP is the only memory-to-memory move instruction; however, oneof the operands must be in the top 64 locations of either X: or Y: memory.The bit-oriented instructions that use I/O short addressing (BCHG, BCLR, BSET, BTST,JCLR, JSCLR, JSET, and JSSET) can also be used to address individual bits for fasterI/O processing.
The digital signal processor (DSP) does not have a hardware data strobeto strobe data out of the GPIO port. If a strobe is needed, it can be implemented usingsoftware to toggle one of the GPIO pins.5-6PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.GENERAL PURPOSE I/O CONFIGURATIONFreescale Semiconductor, Inc...2316 15870X:$FFFFINTERRUPT PRIORITY REGISTER (IPR)X:$FFFEPORT A — BUS CONTROL REGISTER (BCR)X:$FFFDPLL CONTROL REGISTERX:$FFFCOnCE GDB REGISTERX:$FFFBRESERVEDX:$FFFARESERVEDX:$FFF9RESERVEDX:$FFF8RESERVEDX:$FFF7RESERVEDX:$FFF6SCI HI - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF5SCI MID - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF4SCI LOW - REC/XMIT DATA REGISTER (SRX/STX)X:$FFF3SCI TRANSMIT DATA ADDRESS REGISTER (STXA)X:$FFF2SCI CONTROL REGISTER (SCCR)X:$FFF1SCI INTERFACE STATUS REGISTER (SSR)X:$FFF0SCI INTERFACE CONTROL REGISTER (SCR)X:$FFEFSSI RECIEVE/TRANSMIT DATA REGISTER (RX/TX)X:$FFEESSI STATUS/TIME SLOT REGISTER (SSISR/TSR)X:$FFEDSSI CONTROL REGISTER B (CRB)X:$FFECSSI CONTROL REGISTER A (CRA)X:$FFEBHOST RECEIVE/TRANSMIT REGISTER (HRX/HTX)X:$FFEARESERVEDX:$FFE9HOST STATUS REGISTER (HSR)X:$FFE8HOST CONTROL REGISTER (HCR)X:$FFE7RESERVEDX:$FFE6RESERVEDX:$FFE5PORT C — DATA REGISTER (PCD)X:$FFE4PORT B — DATA REGISTER (PBD)X:$FFE3PORT C — DATA DIRECTION REGISTER (PCDDR)X:$FFE2PORT B — DATA DIRECTION REGISTER (PBDDR)X:$FFE1PORT C — CONTROL REGISTER (PCC)X:$FFE0PORT B — CONTROL REGISTER (PBC)X:$FFDFTIMER COUNT REGISTER (TCR)X:$FFDETIMER CONTROL/STATUS REGISTER (TCSR)X:$FFC0RESERVED= Read as random number; write as don’t care.Figure 5-5 On-Chip Peripheral Memory MapMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5-7Freescale Semiconductor, Inc.GENERAL PURPOSE I/O CONFIGURATION•MOVE#$0,X:$FFE0;Select Port B to be general-purpose I/OMOVE#$7F00,X:$FFE2;Select pins PB0–PB7 to be inputs;and pins PB8–PB14 to be outputs••MOVEP #data_out,X:$FFE4Freescale Semiconductor, Inc...MOVEP X:$FFE4,#data_in;Put bits 8–14 of “data_out” on pins;PB8–PB14 bits 0–7 are ignored;Put PB0–PB7 in bits 0–7 of “data_in”Figure 5-6 Instructions to Write/Read Parallel Data with Port BFigure 5-7 details the process of programming Port B as GPIO.
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