Сигнальный МП Motorola DSP56002 (1086189), страница 18
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After the DSP completes the current cycle (an internally executed instruction with orwithout wait states), BG will be deasserted. When BG is deasserted, the A0-A15, PS, DS, X/Y,and RD, WR lines will be driven. However, the data lines will remain in three-state. All signalsare now ready for a normal external access.During the wait state (see Section 7 in the DSP56000 Family Manual), the BR and BGcircuits remain active. However, the port is inactive - the control signals are deasserted,the data signals are inputs, and the address signals remain as the last address read orwritten. When BR is asserted, all signals are three-stated (high impedance).
Table 4-3shows the status of BR and BG during the wait state.Table 4-3 BR and BG During WAITSignalMOTOROLABefore BRAssertedWhile BGAssertedAfter BRDeassertedPORT AAfter Return toNormal State(BG Deasserted)For More Information On This Product,Go to: www.freescale.comAfter FirstExternal Access4 - 17Freescale Semiconductor, Inc.BUS ARBITRATION AND SHARED MEMORYFreescale Semiconductor, Inc...4.7.1Bus Arbitration Using Only BR and BG With Internal ControlPerhaps the simplest example of a shared memory system using a DSP56002 is shownin Figure 4-12.
The bus arbitration is performed within the DSP#2 by using software.DSP#2 controls all bus operations by using I/O pin OUT2 to three-state its own port Aand by never accessing port A without first calling the subroutine that arbitrates the bus.When the DSP#2 needs to use external memory, it uses I/O pin OUT1 to request busaccess and I/O pin IN1 to read bus grant. DSP#1 does not need any extra code for busarbitration since the BR and BG hardware handles its bus arbitration automatically.
Theprotocol for bus arbitration is as follows:At reset: DSP#2 sets OUT2=0 (BR#2=0) and OUT1=1 (BR#1=1), which gives DSP#1access to the bus and suspends DSP#2 bus access.When DSP#2 wants control of the memory, the following steps are performed (see Figure 4-13):1. DSP# 2 sets OUT1=0 (BR#1=0).2. DSP# 2 waits for IN1=0 (BG#1=0 and DSP#1 off the bus).3. DSP#2 sets OUT2=1 (BR#2=1 to let DSP#2 control the bus).4. DSP#2 accesses the bus for block transfers, etc. at full speed.5.
To release the bus, DSP#2 sets OUT2=0 (BR#2=0) after the last externalaccess.6. DSP#2 then sets OUT1=1 (BR#1=1) to return control of the bus to DSP#1.7. DSP#1 then acknowledges mastership by deasserting BG#1.4.7.2Bus Arbitration Using BN, BR, and BG With External ControlFigure 4-14 can be implemented with external bus arbitration logic, which will save processing capacity on the DSPs and can make bus access much faster at a cost of additional hardware. The bus arbitration logic takes control of the external bus by deassertingan enable signal (E1, E2, and E3) to all DSPs, which will then acknowledge by grantingthe bus (BG=0). When a DSP (DSP#1 in Figure 4-14) needs the bus, it will enter theWAIT state with BN asserted. If DSP#1 has highest priority, the arbitration logic grantsthe bus to DSP#1 by asserting E1 (E2 for DSP#2; E3 for DSP#3) to let the DSP knowthat it can have the bus. DSP#1 will then deassert BG to tell the arbiter it has taken control of the bus.
When the DSP no longer needs to make an external access it will deassert BN and the arbiter deasserts E1, after which the DSP deasserts BG.4 - 18PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.BUS ARBITRATION AND SHARED MEMORYBROUT2BROUT1BGIN1Freescale Semiconductor, Inc...CONTROLCONTROLA0 - A15A0 - A15D0 - D23D0 - D23DSP56002 #1DSP56002 #2BUS ARBITERCADMEMORYBANKFigure 4-12 Bus Arbitration Using Only BR and BG with Internal ControlOUT1IN1OUT2DATATRANSFERREDHERE1234567Figure 4-13 Two DSPs with External Bus Arbitration TimingMOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4 - 19Freescale Semiconductor, Inc.BUS ARBITRATION AND SHARED MEMORYSYSTEM MEMORY32K x 24 X DATA RAM32K x 24 Y DATA RAM32K x 24 PROGRAM RAMFreescale Semiconductor, Inc...ADDRESSDATACONTROLADDRESS16DATA24CONTROLADC5ADCADCDSP56002 #1DSP56002 #2DSP56002 #3BG BR BNBG BR BNBG BR BNA1 E1 BR1A2 E2 BR2A3 E3 BR3BUS ARBITRATION LOGIC WITH PRIORITY ENCODERFigure 4-14 Bus Arbitration Using BN, BR, and BG with External Control4.7.3Bus Arbitration Using BR and BG, and WT and BS With No OverheadBy using the circuit shown in Figure 4-15, two DSPs can share memory with hardwarearbitration that requires no software on the part of the DSPs.
The protocol for bus arbitration in Figure 4-15 is as follows:At RESET assume DSP#1 is not making external accesses so that BR#2 is deasserted.Hence, BG of DSP#2 is deasserted, which three-states the buffers, giving DSP#2 controlof the memory.4 - 20PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.BUS ARBITRATION AND SHARED MEMORYMEMORYDFreescale Semiconductor, Inc...DSP #1ACTHREE-STATEBUFFERDSP #2D0 - D23D0 - 23A0 - A15A0 - A15RD, WR,RD, WR,DS, PS, X/YDS, PS, X/YDIRBSWTENABLEBGBRFigure 4-15 Bus Arbitration Using BR and BG,and WT and BS with No OverheadWhen DSP#1 wants control of the memory the following steps are performed (see Figure 4-16):1. DSP#1 makes an external access, thereby asserting BS, which asserts WT(causing DSP#1 to execute wait states in the current cycle) and assertsDSP#2 BR (requesting that DSP#2 release the bus).2.
When DSP#2 finishes its present bus cycle, it three-states its bus drivers andasserts BG. Asserting BG enables the three-state buffers, placing the DSP#1signals on the memory bus. Asserting BG also deasserts WT, which allowsDSP#1 to finish its bus cycle.3. When DSP#1’s memory cycle is complete, it releases BS, which deassertsBR. DSP#2 then deasserts BG, three-stating the buffers and allowing DSP#2to access the memory bus.MOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4 - 21Freescale Semiconductor, Inc.BUS ARBITRATION AND SHARED MEMORYBSWTBRFreescale Semiconductor, Inc...BG12DATA TRANSFERREDBETWEEN DSP#1AND MEMORY HERE3Figure 4-16 Two DSPs with External Bus Arbitration Timing4.7.4Signaling Using SemaphoresFigure 4-17 shows a more sophisticated shared memory system that uses external arbitration with both local external memory and shared memory.
The four semaphores arebits in one of the words in each shared memory bank used by software to arbitrate memory use. Semaphores are commonly used to indicate that the contents of the semaphore’s memory blocks are being used by one processor and are not available for use byanother processor. Typically, if the semaphore is cleared, the block is not allocated to aprocessor; if the semaphore is set, the block is allocated to a processor.Without semaphores, one processor may try to use data while it is being changed byanother processor, which may cause errors.
This problem can occur in a shared memorysystem when separate test and set instructions are used to “lock” a data block for use bya single processor.The correct procedure is to test the semaphore and then set the semaphore if it wasclear to lock and gain exclusive use of the data block. The problem occurs when the second processor acquires the bus and tests the semaphore after the first processor teststhe semaphore but before the first processor can lock the data block. The incorrectsequence is:1.
the first processor tests the semaphore and sees that the block is available2. the second processor then tests the bit and also sees that the block is available3. both processors then set the bit to lock the data4. both proceed to use the data on the assumption that the data cannot bechanged by another processor4 - 22PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.BUS ARBITRATION AND SHARED MEMORY1SEMAPHORE 3BANK 30SEMAPHORE 2BANK 20SEMAPHORE 1BANK 1Freescale Semiconductor, Inc...1SEMAPHORE 0BANK 0DSP56002LOCALMEMORYPROCESSORLOCALMEMORYDSP56002ADDRESSDATA ANDCONTROLBUSESBUSBUFFERBUSBUFFERPROCESSOROR DMAADDRESSDATA ANDCONTROLBUSESARBITRATIONLOGICFigure 4-17 Signaling Using SemaphoresThe DSP56K processor series has a group of instructions designed to prevent this problem.
They perform an indivisible read-modify-write operation and do not release the busbetween the read and write (specifically, A0–A15, DS, PS, and X/Y do not change state).Using a read-modify-write operation allows these instructions to test the semaphore and then to set, clear, or change the semaphore without the possibility ofanother processor testing the semaphore before it is changed. The instructions arebit test and change (BCHG), bit test and clear (BCLR), and bit test and set (BSET).(They are discussed in detail in the DSP56000 Family Manual.) The proper way to setthe semaphore to gain exclusive access to a memory block is to use BSET to test thesemaphore and to set it to one.
After the bit is set, the result of the test operation willreveal if the semaphore was clear before it was set by BSET and if the memory block isavailable. If the bit was already set and the block is in use by another processor, the DSPmust wait to access the memory block.MOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4 - 23Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.For More Information On This Product,Go to: www.freescale.comFreescale Semiconductor, Inc.SECTION 5Freescale Semiconductor, Inc...PORT BMOTOROLAFor More Information On This Product,Go to: www.freescale.com5-1Freescale Semiconductor, Inc.SECTION CONTENTSINTRODUCTION .
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