Сигнальный МП Motorola DSP56002 (1086189), страница 13
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When the bit is clear, the PLL is disabled and the chip’s internal clocks are derived from the clock connected to the EXTAL pin. After hardware reset is deasserted, the PINIT pin is ignored.Phase and Frequency Locked (PLOCK) — The PLOCK output originatesfrom the Phase Detector. The chip asserts PLOCK when the PLL is enabledand has locked on the proper phase and frequency of EXTAL.
The PLOCK output is deasserted by the chip if the PLL is enabled and has not locked on theproper phase and frequency. PLOCK is asserted if the PLL is disabled. PLOCKis a reliable indicator of the PLL lock state only after the chip has exited thehardware reset state. During hardware reset, the PLOCK state is determinedby PINIT and by the PLL lock condition.••2.5TIMER/EVENT COUNTER MODULE PINThe bidirectional TIO pin is the pin that provides an interface to the timer/event counter module. When the TIO is used as an input, the module functions as an external event counter,or it measures external pulse width/signal period. When the TIO is used as an output, themodule functions as a timer and the signal on the TIO pin is the timer pulse.
When the timermodule is not using the TIO pin, the TIO can act as a general purpose I/O pin.2 - 14DSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SECTION 3Freescale Semiconductor, Inc...MEMORY MODULESAND OPERATING MODESMOTOROLAFor More Information On This Product,Go to: www.freescale.com3-1Freescale Semiconductor, Inc.SECTION CONTENTSMEMORY MODULES AND OPERATING MODES .
. . . . . . . . . . . . . . . . . . 3-33.2DSP56002 DATA AND PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . 3-33.3DSP56002 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . . . . 3-43.4DSP56002 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.5DSP56002 INTERRUPT PRIORITY REGISTER.
. . . . . . . . . . . . . . . . . . . . 3-123.6DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR . . 3-13Freescale Semiconductor, Inc...3.13-2MEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.MEMORY MODULES AND OPERATING MODESFreescale Semiconductor, Inc...3.1MEMORY MODULES AND OPERATING MODESThe memory of the DSP56002 can be partitioned in several ways to provide high-speedparallel operation and additional off-chip memory expansion.
Program and data memoryare separate, and the data memory is, in turn, divided into two separate memory spaces,X and Y. Both the program and data memories can be expanded off-chip. There are alsotwo on-chip data read-only memories (ROMs) that can overlay a portion of the X and Ydata memories, and a bootstrap ROM that can overlay part of the program random-access memory (RAM). The data memories are divided into two independent spaces to workwith the two address arithmetic logic units (ALUs) to feed two operands simultaneously tothe data ALU.The DSP operating modes determine the memory maps for program and data memoriesand the start-up procedure when the DSP leaves the reset state.
This section describesthe DSP56002 Operating Mode Register (OMR), its operating modes and their associatedmemory maps, and discusses how to set and reset operating modes.This section also includes details of the interrupt vectors and priorities and describes theeffect of a hardware reset on the PLL multiplication factor.3.2DSP56002 DATA AND PROGRAM MEMORYThe DSP56002 has 512 words of program RAM, 64 words of bootstrap ROM, 256 wordsof RAM and 256 words of ROM for each of the X and Y internal data memories.
The memory maps are shown in Section Figure 3-1 DSP56002 Memory Maps.3.2.1Program MemoryThe DSP56002 has 512 words of program RAM and 64 words of factory-programmedbootstrap ROM.The bootstrap ROM is programmed to perform the bootstrap operation from the memoryexpansion port (port A), from the host interface, or from the SCI.
It provides a convenient,low cost method of loading the program RAM with a user program after power-on reset.The bootstrap ROM activity is controlled by the MA, MB, and MC bits in the OMR (see 3.3DSP56002 OPERATING MODE REGISTER (OMR) for a complete explanation of theOMR and the DSP56002’s operating modes and memory maps).Addresses are received from the program control logic (usually the program counter) overthe PAB.
Program memory may be written using the program memory (MOVEM) instructions. The interrupt vectors are located in the bottom 128 locations ($0000-$007F) ofprogram memory. Program memory may be expanded to 64K off-chip.MOTOROLAMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.com3-3Freescale Semiconductor, Inc.DSP56002 OPERATING MODE REGISTER (OMR)Freescale Semiconductor, Inc...3.2.2X Data MemoryThe on-chip X data RAM is a 24-bit-wide, static internal memory occupying the lowest 256locations (0–255) in X memory space. The on-chip X data ROM occupies locations 256–511 in the X data memory space and is controlled by the DE bit in the OMR.
(See the explanation of the DE bit in Section 3.3.2 Data ROM Enable (Bit 2). Also, see Figure 31.)The on-chip peripheral registers occupy the top 64 locations of the X data memory($FFC0–$FFFF). The 16-bit addresses are received from the XAB, and 24-bit data transfers to the data ALU occur on the XDB. The X memory may be expanded to 64K off-chip.3.2.3Y Data MemoryThe on-chip Y data RAM is a 24-bit-wide internal static memory occupying the lowest 256locations (0–255) in the Y memory space. The on-chip Y data ROM occupies locations256–511 in Y data memory space and is controlled by the DE and YD bits in the OMR.(See the explanations of the DE and YD bits in Sections Section 3.3.2 Data ROM Enable (Bit 2) and Section 3.3.3 Internal Y Memory Disable Bit (Bit 3), respectively. Also,see Figure 3-1.) The 16-bit addresses are received from the YAB, and 24-bit data transfers to the data ALU occur on the YDB.
Y memory may be expanded to 64K off-chip.Note: The off-chip peripheral registers should be mapped into the top 64 locations ($FFC0–$FFFF) to take advantage of the move peripheral data (MOVEP) instruction.3.3DSP56002 OPERATING MODE REGISTER (OMR)Operating modes determine the memory maps for program and data memories, and thestart-up procedure when the DSP leaves the reset state. The processor samples the MODA, MODB, and MODC pins as it leaves the reset state, establishes the initial operatingmode, and writes the operating mode information to the Operating Mode Register. Whenthe processor leaves the reset state, the MODA and MODB pins become general-purposeinterrupt pins, IRQA and IRQB, respectively, and the MODC pin becomes the nonmaskable interrupt pin NMI.The OMR is a 24-bit register (only six bits are defined) that controls the current operatingmode of the processor.
It is located in the DSP56002’s Program Control Unit (describedin Section 5 of the DSP56000 Family Manual). The OMR bits are only affected by processor reset and by the ANDI, ORI, MOVEC, BSET, BCLR, and BCHG instructions, whichdirectly reference the OMR. The OMR format for the DSP56002 is shown in Figure 3-2OMR Format.3-4MEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.DSP56002 OPERATING MODE REGISTER (OMR)$FFFF$FFFF$FFFFPROGRAMMEMORYSPACEX DATAMEMORYSPACEY DATAMEMORYSPACE$7FINTERRUPTVECTORSFreescale Semiconductor, Inc...$0$0OPERATING MODE DETERMINESPROGRAM MEMORY AND RESETSTARTING ADDRESSMODE 0MC=0 MB=0 MA=0MODE 3MODE 2MC=0 MB=1 MA=0 MC=0 MB=1 MA=1$FFFF$FFFF$FFFFEXTERNALEXTERNAL$003F INTERRUPTS$0$01FFINTERNALRAM$003FRESETINTERNAL P: RAMINTERNAL RESET$003F INTERRUPTSINTERRUPTS$0$0RESET$01FF INTERNALX ROM +A-LAW/LIN$017F INTERNALX ROM +MU-LAW/LIN$00FF INTERNAL$0ON-CHIPPERIPHERAL MAPHOST COMMANDSDE = 0YD = 0$FFFF ON-CHIP$FFC0 PERIPHERALSEXTERNALX DATAMEMORYEXTERNALY DATAMEMORYEXTERNALY DATAMEMORYINTERNALY ROMFULLSINE-WAVEINTERNALY RAM$00FF INTERNALINTERNALX RAMY RAM$0DATA ROMS DISABLEDDE = 1YD = 1$FFFF ON-CHIP$FFC0 PERIPHERALS$FFBFEXTERNALPERIPHERALSEXTERNALPERIPHERALSDE = 0YD = 1$FFFF ON-CHIP$FFC0 PERIPHERALSEXTERNALPERIPHERALS$FFFFINTERRUPT PRIORITYBUS CONTROLSCI INTERFACESSI INTERFACEHOST INTERFACEPARALLEL I/0 INTERFACETIMERILLEGAL INSTRUCTION INT.TIMER INTERRUPTHOST COMMANDSSCI INTERRUPTSSSI INTERRUPTSEXTERNAL INTERRUPTSSWI INTERRUPTTRACE INTERRUPTSTACK ERROR INTERRUPT$0000 RESETX RAMEXTERNALPERIPHERALSDATA ROMS ENABLEDINTERNAL P: RAM NO INTERNAL P: RAMEXTERNAL RESET EXTERNAL RESETINTERRUPT MAP$007F$0040$003E$003C$003A$0024EXTERNALX DATAMEMORYEXTERNAL$01FFINTERNALRAMDE = 1YD = 0$FFFF ON-CHIP$FFC0 PERIPHERALS$FFBFRESET$E000$01FF$0DE and YD BITS IN THE OMR DETERMINETHE X AND Y DATA MEMORY MAPS$FFDERESERVED$FFC0EXTERNALX DATAMEMORYEXTERNALY DATAMEMORYEXTERNALY DATAMEMORY$01FFINTERNALX ROM +A-LAW/LIN$017F INTERNALX ROM +MU-LAW/LIN$00FF INTERNAL$0X RAM$00FF INTERNALX RAM$0NOTE: Addresses $FFC0–$FFFF in X data memoryare NOT available externallyFigure 3-1 DSP56002 Memory MapsMOTOROLAMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.com3-5Freescale Semiconductor, Inc.DSP56002 OPERATING MODE REGISTER (OMR)238*76543*SD*MC YD210DE MB MAOPERATING MODES A, BDATA ROM ENABLEINTERNAL Y MEMORY DISABLEOPERATING MODE CRESERVEDSTOP DELAYFreescale Semiconductor, Inc...RESERVEDRESERVEDFigure 3-2 OMR Format3.3.1Chip Operating Mode (Bits 0 and 1)The chip operating mode bits, MB and MA, together with MC, define the program memory maps and the operating mode of the DSP56002.
On processor reset, MB and MA areloaded from the external mode select pins, MODB and MODA, respectively. After theDSP leaves the reset state, MB and MA can be changed under software control.3.3.2Data ROM Enable (Bit 2)The DE bit enables the two, on-chip, 256X24 data ROMs located between addresses$0100–$01FF in the X and Y memory spaces. When DE is cleared, the $0100–$01FFaddress space is part of the external X and Y data spaces, and the on-chip data ROMsare disabled.
Hardware reset clears the DE bit.3.3.3Internal Y Memory Disable Bit (Bit 3)Bit 3 is defined as Internal Y Memory Disable (YD). When set, all Y Data Memory addresses are considered to be external, disabling access to internal Y Data Memory. Whencleared, internal Y Data Memory may be accessed according to the state of the DE controlbit. The content of the internal Y Data Memory is not affected by the state of the YD bit.The YD bit is cleared during hardware reset.Figure 3-1 DSP56002 Memory Maps shows a graphic representation of the DE and YDbit effects on the X and Y data memory maps.
Table 3-1 also compares the DE and YDeffects on the memory maps.3-6MEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.DSP56002 OPERATING MODESFreescale Semiconductor, Inc...Table 3-1 Memory Mode BitsDEYDData Memory00Internal ROMs Disabled and their addresses are part ofExternal Memory01Internal X Data ROM is Disabled and is part of ExternalMemory.
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