Сигнальный МП Motorola DSP56002 (1086189), страница 15
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The solution is to modify the DSP56001 program to set MC-MA = 101.3.4.7Bootstrap From SCI (Mode 6)In this mode, the Bootstrap ROM is enabled and the bootstrap program is executed. Theinternal and/or external program RAM is loaded from the SCI serial interface. The numberof program words to load and the starting address must be specified. The SCI bootstrapcode expects to receive 3 bytes specifying the number of program words, 3 bytes specifying the address from which to start loading the program words, and then 3 bytes for eachprogram word to be loaded. The number of words, the starting address and the programwords are received least significant byte first, followed by the mid-, and then by the mostsignificant byte.
After receiving the program words, program execution starts at the address where the first instruction was loaded. The SCI is programmed to work inasynchronous mode with 8 data bits, 1 stop bit, and no parity. The clock source is externaland the clock frequency must be 16x the baud rate. After each byte is received, it is echoed back through the SCI transmitter.3.4.8Reserved (Mode 7)This mode is reserved for future definition.
If selected, the processor defaults to Mode 6.3.5DSP56002 INTERRUPT PRIORITY REGISTERSection 7 of the DSP56000 Family Manual describes interrupt (exception) processing indetail. It discusses interrupt sources, interrupt types, and interrupt priority levels (IPL).Interrupt priority levels for each on-chip peripheral device and for each external interruptsource can be programmed under software control by writing to the interrupt priority register. Level 3 interrupts are nonmaskable, and interrupts of levels 0-2 are maskable.The DSP56002 Interrupt Priority Register (IPR) configuration is shown in Section Figure 3-4 DSP56002 Interrupt Priority Register (IPR). The starting addresses of interruptvectors in the DSP56002 are defined as shown in Section Table 3-4 Interrupt Vectors,while the relative priorities of exceptions within the same IPL are defined as shown inSection Table 3-5 Exception Priorities Within an IPL).3 - 12MEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTOR11109876HPL1 HPL0543210IBL2IBL1IBL0IAL2IAL1IAL0IRQA MODEIRQB MODERESERVEDHOST IPLFreescale Semiconductor, Inc...232221201918171615141312TIL1 TIL0 SCL1 SCL0 SSL1 SSL0SSI IPLSCI IPLTIMER IPLRESERVEDReserved, read as zero and should be written with zero for future compatibility.Figure 3-4 DSP56002 Interrupt Priority Register (IPR)3.6DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTORSection 9 of the DSP56000 Family Manual discusses the details of the PLL.
The multiplication factor determines the frequency at which the Voltage Controlled Oscillator (VCO)will oscillate. The user sets the multiplication factor by writing to the MF0-MF11 bits in thePLL control register.The DSP56002 PLL multiplication factor is set to 1 during hardware reset, which meansthat the Multiplication Factor Bits MF0-MF11 in the PLL Control Register (PCTL) are setto $000.MOTOROLAMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.com3 - 13Freescale Semiconductor, Inc.DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTORFreescale Semiconductor, Inc...Table 3-4 Interrupt Vectors3 - 14InterruptStarting AddressIPLP:$00003Hardware RESETP:$00023Stack ErrorP:$00043TraceP:$00063SWIP:$00080-2IRQAP:$000A0-2IRQBP:$000C0-2SSI Receive DataP:$000E0-2SSI Receive Data With Exception StatusP:$00100-2SSI Transmit DataP:$00120-2SSI Transmit Data with Exception StatusP:$00140-2SCI Receive DataP:$00160-2SCI Receive Data with Exception StatusP:$00180-2SCI Transmit DataP:$001A0-2SCI Idle LineP:$001C0-2SCI TimerP:$001E3P:$00200-2Host Receive DataP:$00220-2Host Transmit DataP:$00240-2Host Command (Default)P:$00260-2Available for Host CommandP:$003A0-2Available for Host CommandP:$003C0-2TimerP:$003E3P:$00400-2Available for Host CommandP:$007E0-2Available for Host CommandInterrupt SourceNMIIllegal InstructionMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.DSP56002 PHASE-LOCKED LOOP (PLL) MULTIPLICATION FACTORTable 3-5 Exception Priorities Within an IPLPriorityExceptionLevel 3 (Nonmaskable)HighestHardware RESETIllegal InstructionNMIFreescale Semiconductor, Inc...Stack ErrorTraceLowestSWILevels 0, 1, 2 (Maskable)HighestIRQA (External Interrupt)IRQB (External Interrupt)Host Command InterruptHost Receive Data InterruptHost Transmit Data InterruptSSI RX Data with Exception InterruptSSI RX Data InterruptSSI TX Data with Exception InterruptSSI TX Data InterruptSCI RX Data with Exception InterruptSCI RX Data InterruptSCI TX Data with Exception InterruptSCI TX Data InterruptSCI Idle Line InterruptSCI Timer InterruptLowestMOTOROLATimer InterruptMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.com3 - 15Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.For More Information On This Product,Go to: www.freescale.comFreescale Semiconductor, Inc.SECTION 4Freescale Semiconductor, Inc...PORT AMOTOROLAFor More Information On This Product,Go to: www.freescale.com4-1Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...SECTION CONTENTS4.1INTRODUCTION .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.2PORT A INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.3PORT A TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94.4PORT A WAIT STATES. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134.5BUS CONTROL REGISTER (BCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134.6BUS STROBE AND WAIT PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154.7BUS ARBITRATION AND SHARED MEMORY. . . . .
. . . . . . . . . . . . . . . . . 4-164-2PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.INTRODUCTION4.1INTRODUCTIONPort A provides a versatile interface to external memory, allowing economical connectionwith fast memories/devices, slow memories/devices, and multiple bus master systems.Freescale Semiconductor, Inc...Port A has two power-reduction features. It can access internal memory spaces, togglingonly the external memory signals that need to change, thereby eliminating unneededswitching current. Also, if conditions allow the processor to operate at a lower memoryspeed, wait states can be added to the external memory access to significantly reducepower while the processor accesses those memories.4.2PORT A INTERFACEThe DSP56002 processor can access one or more of its memory sources (X data memory, Y data memory, and program memory) while it executes an instruction.
The memorysources may be either internal or external to the DSP. Three address buses (XAB, YAB,and PAB) and four data buses (XDB, YDB, PDB, and GDB) are available for internalmemory accesses during one instruction cycle. Port A’s one address bus and one databus are available for external memory accesses.If all memory sources are internal to the DSP, one or more of the three memory sourcesmay be accessed in one instruction cycle (i.e., program memory access or program memory access plus an X, Y, XY, or L memory reference). However, when one or more of thememories are external to the chip, memory references may require additional instructioncycles because only one external memory access can occur per instruction cycle.If an instruction cycle requires more than one external access, the processor will makethe accesses in the following priority: X memory, Y memory, and program memory.
Ittakes one instruction cycle for each external memory access – i.e., one access can beexecuted in one instruction cycle, two accesses take two instruction cycles, etc. Since theexternal data bus is only 24 bits wide, one XY or long external access will take two instruction cycles. The 16-bit address bus can sustain a rate of one memory access perinstruction cycle (using no-wait-state memory which is discussed in 4.4 PORT A WAITSTATES).Figure 4-1 shows the port A signals divided into their three functional groups: address bussignals (A0-A15), data bus signals (D0-D15), and bus control.
The bus control signals canbe subdivided into three additional groups: read/write control (RD and WR), addressspace selection (including program memory select (PS), data memory select (DS), andX/Y select) and bus access control (BN, BR, BG, WT, BS).The read/write controls can act as decoded read and write controls, or, as seen in Figure4-2, Figure 4-3, and Figure 4-4, the write signal can be used as the read/write control, andthe read signal can be used as an output enable (or data enable) control for the memory.MOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4-3Freescale Semiconductor, Inc.PORT A INTERFACE16 - BIT INTERNALADDRESS BUSESX ADDRESS (XA)16Y ADDRESS (YA)EXTERNALADDRESS BUSSWITCHEXTERNALADDRESS BUSA0 - A15Freescale Semiconductor, Inc...PROGRAM ADDRESS (PA)24 - BIT INTERNALDATA BUSESX DATA (XD)24Y DATA (YD)EXTERNALDATA BUSD0 - D23EXTERNALDATA BUSSWITCHPROGRAM DATA (PD)GLOBAL DATA (GD)BUS CONTROL SIGNALSEXTERNALBUS CONTROLLOGICRD –- READ ENABLEWR – WRITE ENABLEPS – PROGRAM MEMORY SELECTDS – DATA MEMORY SELECTX/Y – X MEMORY/Y MEMORY SELECTBN –- BUS NEEDEDBR – BUS REQUESTBG – BUS GRANTWT – BUS WAITBS – BUS STROBEFigure 4-1 Port A SignalsDecoding in such a way simplifies connection to high-speed random-access memories4-4PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.PORT A INTERFACEVCC+5 VVSSGROUND16ADDRESS BUSA0 - A15PROGRAM MEMORYADDRESS24Freescale Semiconductor, Inc...DATA BUSD0 - D23DATADSP56002BUSCONTROLRDOEWRR/WPSCS24 BIT x N WORDSDSX/YBNBRBGWTBSFigure 4-2 External Program Space(RAMs).
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