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The memory reference signals (PS, DS, and X/Y) are deasserted (heldhigh) during periods of no bus activity, and the data signals are three-stated.For read-modify-write instructions such as BSET, the address and memoryreference signals remain active for the complete composite (i.e., two Icyc)instruction cycle.MOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4 - 11Freescale Semiconductor, Inc.PORT A TIMINGPORT A BUS CONTROL REGISTER (BCR)EXTERNALX MEMORY15X:$FFFEEXTERNALY MEMORY12110100EXTERNALP MEMORY87EXTERNALI/0 MEMORY410003010101101D/ACONVERTERCSWRD CSRD350 ns(13 WAIT STATES)A15A0 - A15A15D0 - D23INTERNALMEMORY(0 WAIT STATES)Freescale Semiconductor, Inc...DA/DCONVERTER40 MHzDSP560026242 - 156242 - 152764 - 2527256 - 302764 - 2527256 - 306242 - 152764 - 2527256 - 308K x 24X RAM150 ns8K x 24Y ROM250 ns32K x 24P ROM300 ns(4 WAIT STATES)(8 WAIT STATES)(10 WAIT STATES)CS CS WE OECSOECEOEX/YDSWRRDPSFigure 4-8 Mixed-Speed Expanded System4 - 12PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.PORT A WAIT STATESFreescale Semiconductor, Inc...Figure 4-8 shows an example of mixing different memory speeds and memory-mappedperipherals in different address spaces.
The internal memory uses no wait states, X: memoryuses two wait states, Y: memory uses four wait states, P: memory uses five wait states, andthe analog converters use 14 wait states. Controlling five different devices at five differentspeeds requires only one additional logic package.
Half the gates in that package are usedto map the analog converters to the top 64 memory locations in Y: memory.4.4PORT A WAIT STATESThe DSP56002 features two methods to allow the user to accommodate slow memoryby changing the port A bus timing. The first method uses the bus control register (BCR),which allows a fixed number of wait states to be inserted in a given memory access to alllocations in each of the four memory spaces: X, Y, P, and I/O. The second method usesthe bus strobe (BS) and bus wait (WT) facility, which allows an external device to insertan arbitrary number of wait states when accessing either a single location or multiplelocations of external memory or I/O space. Wait states are executed until the externaldevice releases the DSP to finish the external memory cycle.Table 4-2 Wait State ControlBCRContentsWT0Deasserted0Asserted>0Deasserted>0AssertedNumber of Wait States Generated02 (minimum)Equals value in BCRMinimum equals 2 or value in BCR.Maximum is determined by BCR or WT,whichever is larger.4.5BUS CONTROL REGISTER (BCR)The BCR determines the expansion bus timing by controlling the timing of the bus interface signals, RD and WR, and the data output lines.
It is a memory mapped registerlocated at X:$FFFE. Each of the memory spaces in Figure 4-9 (X data, Y data, programdata, and I/O) has its own 4-bit BCR, which can be programmed for inserting up to 15wait states (each wait state adds one-half instruction cycle to each memory access – i.e.,50 ns for a 20-Mhz clock). In this way, external bus timing can be tailored to match thespeed requirements of the different memory spaces. On processor reset, the BCR ispreset to all ones (15 wait states).
This allows slow memory to be used for boot strapping. The BCR needs to be set appropriately for the memory being used or the processorwill insert 15 wait states between each memory fetch and cause the DSP to run slow.MOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4 - 13Freescale Semiconductor, Inc.BUS CONTROL REGISTER (BCR)15X:$FFFE12EXTERNALX MEMORY *118EXTERNALY MEMORY *4EXTERNALP MEMORY *$FFFF$FFFF$FFFEFreescale Semiconductor, Inc...7$FFFFBUS CONTROL REGISTEREXTERNALPERIPHERALS$FFC0$FFC0EXTERNALX DATAMEMORY$200$200INTERNALPROGRAMRAM$100EXTERNALY DATAMEMORY$200INTERNALX ROM$100INTERNALX RAM00PROGRAMMEMORY SPACE0EXTERNALI/0 MEMORY *ON-CHIP PERIPHERALSEXTERNALPROGRAMMEMORY3INTERNALY ROMINTERNALY RAM0X DATAMEMORYSPACEY DATAMEMORYSPACE* Zero to 15 wait states can be inserted into each external memory access.Figure 4-9 Bus Control RegisterFigure 4-9 illustrates which of the four BCR subregisters affect which external memoryspace.
All the internal peripheral devices are memory mapped, and their control registersreside between X:$FFC0 and X:$FFFF.To load the BCR the way it is shown in Figure 4-8, execute a “MOVEP #$48AD,X:$FFFE” instruction. Or, change the individual bits in one of the four subregisters byusing the BSET and BCLR instructions which are detailed in the DSP56000 Family Manual, SECTION 6 and APPENDIX A.Figure 4-8 shows an example of mixing different memory speeds and memory-mappedperipherals in different address spaces.
The internal memory uses no wait states, X: memory uses two wait states, Y: memory uses four wait states, P: memory uses five wait states,and the analog converters use 14 wait states. Controlling five different devices at five different speeds requires only one additional logic package. Half the gates in that packageare used to map the analog converters to the top 64 memory locations in Y: memory.4 - 14PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.BUS STROBE AND WAIT PINSOPERATING MODE REGISTER76543210EMSD000DEMBMASET EM = 1VCCVSS+5 V GROUNDT0Freescale Semiconductor, Inc...DSP56000/DSP56001T1T2TWTWTWTWT3T016ADDRESS BUSA0 - A15A0 - A15, D0 - D23, PS, DS, X/Y24DATA BUSD0 - D23BUSCONTROLWT ISSAMPLEDWT ISSAMPLEDWT ISSAMPLEDRDWRPSDSX/YWTT3BSFigure 4-10 Bus Strobe/Wait SequenceAdding wait states to external memory accesses can substantially reduce power requirements.
Consult the DSP56002 Technical Data Sheet (DSP56002/D) for specific powerconsumption requirements.4.6BUS STROBE AND WAIT PINSThe ability to insert wait states using BS and WT provides a means to connect asynchronous devices to the DSP, allows devices with differing timing requirements to reside in thesame memory space, allows a bus arbiter to provide a fast multiprocessor bus access, andprovides another means of halting the DSP at a known program location with a fast restart.The timing of the BS and WT pins is illustrated in Figure 4-10. Every external access, BSis asserted concurrently with the address lines in T0. BS can be used by external wait-MOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4 - 15Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...BUS ARBITRATION AND SHARED MEMORYstate logic to establish the start of an external access.
BS is deasserted in T3 of eachexternal bus cycle, signaling that the current bus cycle will complete. Since the WT signalis internally synchronized, it can be asserted asynchronously with respect to the systemclock. The WT signal should only be asserted while BS is asserted. Asserting WT whileBS is deasserted will give indeterminate results.
However, for the number of inserted waitstates to be deterministic, WT timing must satisfy setup and hold timing with respect to thenegative-going edge of EXTAL. The setup and hold times are provided in the DSP56002Advance Information Data Sheet (DSP56002/D). The timing of WR is controlled by theBCR and is independent of WT. The minimum number of wait states that can be insertedusing the WT pin is two. The BCR is still operative when using BS and WT and definesthe minimum number of wait states that are inserted.
Table 4-2 summarizes the effect ofthe BCR and WT pin on the number of wait states generated.4.7BUS ARBITRATION AND SHARED MEMORYThe DSP56002 has five pins that control port A. They are bus needed (BN), bus request(BR), bus grant (BG), bus strobe (BS) and bus wait (WT) and they are described in SECTION 2 DSP56002 PIN DESCRIPTIONS.The bus control signals provide the means to connect additional bus masters (which may beadditional DSPs, microprocessors, direct memory access (DMA) controllers, etc.) to the portA bus. They work together to arbitrate and determine what device gets access to the bus.If an external device has requested the external bus by asserting the BR input, and theDSP has granted the bus by asserting BG, the DSP will continue to process as long as itrequires no external bus accesses itself.
If the DSP does require an external access butis not the bus master, it will stop processing and remain in wait states until it regains busownership. The BN pin will have been asserted, and an external device may use BN tohelp “arbitrate”, or decide when to return bus ownership to the chip.Four examples of bus arbitration will be described later in this section: 1) bus arbitrationusing only BR and BG with internal control, 2) bus arbitration using BN, BR, and BG withexternal control, 3) bus arbitration using BR, BG and WT, BS with no overhead, and 4)signaling using semaphores.The BR input allows an external device to request and be given control of the external buswhile the DSP continues internal operations using internal memory spaces.
This allows abus controller to arbitrate a multiple bus-master system. (A bus master can issueaddresses on the bus; a bus slave can respond to addresses on the bus. A single devicecan be both a master and a slave, but can only be one or the other at any given time.)4 - 16PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.BUS ARBITRATION AND SHARED MEMORYBRBGA0 - A15, D0 - D23, PS,DS, X/Y, RD, WRA DIFFERENTBUS MASTERFreescale Semiconductor, Inc...DSP56002BUS MASTERDSP56002BUS MASTERFigure 4-11 Bus Request/Bus Grant SequenceBefore BR is asserted, all port A signals are driven.
When BR is asserted (see Figure 4-11), theDSP will assert BG after the current external access cycle completes and will simultaneouslythree-state (high-impedance) the port A signals (see the DSP56002 Technical Data Sheet(DSP56002/D) for exact timing of BR and BG). The bus is then available to whatever externaldevice has bus mastership. The external device will return bus mastership to the DSP by deasserting BR.
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