Сигнальный МП Motorola DSP56002 (1086189), страница 16
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The program memory select, data memory select, and X/Y select can be considered additional address signals, which extend the directly addressable memory from 64Kwords to 192K words total.Since external logic delay is large relative to RAM timing margins, timing becomes moredifficult as faster DSPs are introduced. The separate read and write strobes used by theDSP56002 are mutually exclusive, with a guard time between them to avoid an instancewhere two data buffers are enabled simultaneously. Other methods using external logicgates to generate the RAM control inputs require either faster RAM chips or externaldata buffers to avoid data bus buffer conflicts.Figure 4-2 shows an example of external program memory.
A typical implementation ofthis circuit would use three-byte-wide static memories and would not require any additional logic. The PS signal is used as the program-memory chip-select signal to enablethe program memory at the appropriate time.Figure 4-3 shows a similar circuit using the DS signal to enable two data memories andMOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4-5Freescale Semiconductor, Inc.PORT A INTERFACEVCC+5 VVSSGROUND16ADDRESS BUSA0 - A1524Freescale Semiconductor, Inc...DATA BUSD0 - D23DATAADDRESSDATAX DATAMEMORY24 BITS x N WORDSDSP56002OER/WCSADDRESSY DATAMEMORY24 BITS x N WORDSCEOER/WCSCEBUSCONTROLRDWRPSDSX/YBNBRBGWTBSFigure 4-3 External X and Y Data Spaceusing the X/Y signal to select between them.
The three external memory spaces (program, X data, and Y data) do not have to reside in separate physical memories; a singlememory can be employed by using the PS, DS, and X/Y signals as additional addresslines to segment the memory into three spaces (see Figure 4-4). Table 4-1 shows howthe PS, DS, and X/Y signals are decoded.If the DSP is in the development mode, an exception fetch to any interrupt vector locationwill cause the X/Y signal to go low when PS is asserted.
This procedure is useful fordebugging and for allowing external circuitry to track interrupt servicing.4-6PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.PORT A INTERFACEPSDSX/YExternal Memory Reference111No Activity101X Data Memory on Data Bus100Y Data Memory on Data Bus011Program Memory on Data Bus (Not an Exception)010External Exception Fetch: Vector or Vector +1(Development Mode Only)00XReserved110ReservedFigure 4-5 shows a system that uses internal program memory loaded from an externalVCC+5 VVSSGROUNDEXTERNALPROGRAMX AND Y MEMORY16A0-A10$3FFFDSP56002A15A14ADDRESS BUSA0 - A15A13Freescale Semiconductor, Inc...Table 4-1 Program and Data Memory Select EncodingCEU14KPROGRAMMEMORY24DATA BUSD0 - D23BUSCONTROLOER/WRDWRPSU2$2FFFCSA122KX DATAMEMORYA11$27FFDSX/Y$2800A11U3BNBR$3000U4BG2KY DATAMEMORYWT$2000BS24 BITSFigure 4-4 Memory SegmentationMOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4-74-8For More Information On This Product,Go to: www.freescale.comPORT AFROM OPENCOLLECTORBUFFERFROMRESETFUNCTIONFROM OPENCOLLECTORBUFFERMBD301*MBD301*MODB/IRQBRESETMODC/NMIX/YRDWRDSD0-D23A0-A10PSDR DSP56002BRHACKWTMODA/IRQACE1181024D0-D232018-55 (3)A0-A9 A10 CS WE OENotes: 1.
*These diodes must be Schottky diodes.2. All resistors are 15KΩ unless noted otherwise.3. When in RESET, IRQA, IRQB and NMI mustbe deasserted by external peripherals.D0-D72716A0-A10Figure 4-5 Port A Bootstrap ROM with X and Y RAMMBD301*+5 VFreescale Semiconductor, Inc...Freescale Semiconductor, Inc.PORT A INTERFACEROM during power-up and splits the data memory space of a single memory bank into X:MOTOROLAFreescale Semiconductor, Inc.PORT A TIMINGFreescale Semiconductor, Inc...and Y: memory spaces.
Although external program memory must be 24 bits, external datamemory does not. Of course, this is application specific. Many systems use 16 or fewer bitsfor A/D and D/A conversion and, therefore, they may only need to store 16, 12, or even eightbits of data. The 24/56 bits of internal precision is usually sufficient for intermediate results.This is a cost saving feature which can reduce the number of external memory chips.4.3PORT A TIMINGThe external bus timing is defined by the operation of the address bus, data bus, and buscontrol pins. The transfer of data over the external data bus is synchronous with the clock.The timing A, B, and C relative to the edges of an external clock (see Figure 4-6 and Figure 4-7) are provided in the DSP56002 Advance Information Data Sheet (DSP56002/D).This timing is essential for designing synchronous multiprocessor systems.
Figure 4-6shows the port A timing with no wait states (wait-state control is discussed in Section 4.4).One instruction cycle equals two clock cycles or four clock phases. The clock phases,which are numbered T0 – T3, are used for timing on the DSP. Figure 4-7 shows the sametiming with two wait states added to the external X: memory access.Four TW clock phases have been added because one wait state adds two T phases andONE INSTRUCTION CYCLEONE CLOCK CYCLET0T1T2T3T0T1T2T3T0T1INTERNAL CLOCK PHASESADDRESS PS, DS, X/YARDBREADCYCLEDATA INWRWRITECYCLECDATA OUTFigure 4-6 Port A Bus Operation with No Wait StatesMOTOROLAPORT AFor More Information On This Product,Go to: www.freescale.com4-9Freescale Semiconductor, Inc.PORT A TIMINGONE INSTRUCTION CYCLETWO WAIT STATESONE CLOCK CYCLET0INTERNAL CLOCK PHASEST1T2TWTWTWTWT3T0T1ADDRESS PS, DS, X/YFreescale Semiconductor, Inc...ARDBREADCYCLEDATA INWRITECYCLEWRCDATA OUTDATA LATCHED HEREFigure 4-7 Port A Bus Operation with Two Wait Statesis equivalent to repeating the T2 and T2 clock phases.
The write signal is also delayedfrom the T1 to the T2 state when one or more wait states are added to ease interfacing tothe port. Each external memory access requires the following procedure:1. The external memory address is defined by the address bus (A0–A15) and thememory reference selects (PS, DS, and X/Y). These signals change in the firstphase (T0) of the bus cycle. Since the memory reference select signals havethe same timing as the address bus, they may be used as additional addresslines. The address and memory reference signals are also used to generatechip-select signals for the appropriate memory chips. These chip-select signals change the memory chips from low-power standby mode to active modeand begin the read access time. This mode change allows slower memories tobe used since the chip-select signals can be address based rather than reador write enable based.
Read and write enable do not become active until afterthe address is valid. See the timing diagrams in the DSP56002 Advance Information Data Sheet (DSP56002/D) for detailed timing information.2. When the address and memory reference signals are stable, the data transfer4 - 10PORT AFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.Freescale Semiconductor, Inc...PORT A TIMINGis enabled by read enable (RD) or write enable (WR). RD or WR is asserted to“qualify” the address and memory reference signals as stable and to performthe read or write data transfer.
RD and WR are asserted in the second phaseof the bus cycle (if there are no wait states). Read enable is typically connected to the output enable (OE) of the memory chips and simply controls theoutput buffers of the chip-selected memory. Write enable is connected to thewrite enable (WE) or write strobe (WS) of the memory chips and is the pulsethat strobes data into the selected memory. For a read operation, RD isasserted and WR remains deasserted.
Since write enable remains negated, amemory read operation is performed. The DSP data bus becomes an input,and the memory data bus becomes an output. For a write operation, WR isasserted and RD remains deasserted. Since read enable remains deasserted,the memory chip outputs remain in the high-impedance state even before writestrobe is asserted. This state assures that the DSP and the chip-selectedmemory chips are not enabled onto the bus at the same time. The DSP databus becomes an output, and the memory data bus becomes an input.3. Wait states are inserted into the bus cycle by a wait-state counter or by asserting WT.
The wait-state counter is loaded from the bus control register. If thevalue loaded into the wait-state counter is zero, no wait states are inserted intothe bus cycle, and RD and WR are asserted as shown in Figure 4-6. If a valueW≠0 is loaded into the wait state counter, W wait states are inserted into thebus cycle. When wait states are inserted into an external write cycle, WR isdelayed from T1 to T2.
The timing for the case of two wait states (W=2) isshown in Figure 4-7.4. When RD or WR are deasserted at the start of T3 in a bus cycle, the data islatched in the destination device – i.e., when RD is deasserted, the DSPlatches the data internally; when WR is deasserted, the external memorylatches the data on the positive-going edge. The address signals remain stable until the first phase of the next external bus cycle to minimize power dissipation.
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