Сигнальный МП Motorola DSP56002 (1086189), страница 12
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This pin’s function is determined by whether the SCLK is in synchronous or asynchronous mode.Inasynchronous mode, this pin is frame sync I/O. For synchronous mode with continuousclock, this pin is serial flag SC1 and operates like the SC0. SC0 and SC1 are independentserial I/O flags but may be used together for multiple serial device selection. SC1 can beprogrammed as a general-purpose I/O pin (PC4) when the SSI SC1 function is not beingused, and it is configured as a GPIO input pin during hardware reset.2.2.7.3Serial Control Two (SC2)The SSI uses this bidirectional pin to control frame synchronization only. As with SC0 andSC1, its function is defined by the SSI operating mode.
SC2 can be programmed as ageneral-purpose I/O pin (PC5) when the SSI SC2 function is not being used, and it is configured as a GPIO input pin during hardware reset.2.2.7.4SSI Serial Clock (SCK)This bidirectional pin provides the serial bit rate clock for the SSI when only one clock isbeing used. SCK can be programmed as a general-purpose I/O pin (PC6) when it is notneeded as an SSI pin, and it is configured as a GPIO input pin during hardware reset.2.2.7.5SSI Receive Data (SRD)This input pin receives serial data into the SSI receive shift register.
SRD can be programmed as a general-purpose I/O pin (PC7) when it is not needed as an SSI pin, and itis configured as a GPIO input pin during hardware reset.2.2.7.6SSI Transmit Data (STD)This output pin transmits serial data from the SSI transmit shift register. STD can be programmed as a general-purpose I/O pin (PC8) when it is not needed as an SSI pin, and itis configured as a GPIO input pin during hardware reset.2.3ON-CHIP EMULATION (OnCE) PINSThe following paragraphs describe the OnCE pins associated with the OnCE controllerand its serial interface.2.3.1Debug Serial Input/Chip Status 0 (DSI/OS0)Serial data or commands are provided to the OnCE controller through the DSI/OS0 pinwhen it is an input. The data received on the DSI pin will be recognized only when theDSP56K has entered the debug mode of operation.
Data is latched on the falling edge ofMOTOROLADSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.com2 - 11Freescale Semiconductor, Inc.ON-CHIP EMULATION (OnCE) PINSthe DSCK serial clock. Data is always shifted into the OnCE serial port most significant bit(MSB) first. When the DSI/OS0 pin is an output, it works in conjunction with the OS1 pinto provide chip status information (see Section 10 ON CHIP EMULATION (OnCE) in theDSP56000 Family Manual). The DSI/OS0 pin is an output when the processor is not indebug mode. When switching from output to input, the pin is three-stated.
During hardware reset, this pin is defined as an output and it is driven low.Freescale Semiconductor, Inc...Note: To avoid possible glitches, an external pull-down resistor should be attached to this pin.2.3.2Debug Serial Clock/Chip Status 1 (DSCK/OS1)The DSCK/OS1 pin supplies the serial clock to the OnCE when it is an input. The serialclock provides pulses required to shift data into and out of the OnCE serial port.
(Data isclocked into the OnCE on the falling edge and is clocked out of the OnCE serial port onthe rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency.The pin is three-stated when it is changing from input to output. When it is an output, it workswith the OS0 pin to provide information about the chip status (see SECTION 10 ON CHIPEMULATION (OnCE) in the DSP56000 Family Manual). It is an output when the chip is notin debug mode.
During hardware reset, this pin is defined as an output and is driven low.Note: To avoid possible glitches, an external pull-down resistor should be attached to this pin.2.3.3Debug Serial Output (DSO)The DSP reads serial data from the OnCE through the DSO output pin, as specified bythe last command received from the external command controller. Data is always shiftedout the OnCE serial port most significant bit (MSB) first.
Data is clocked out of the OnCEserial port on the rising edge of DSCK.The DSO pin also provides acknowledge pulses to the external command controller.When the chip enters the debug mode, the DSO pin will be pulsed low to indicate (acknowledge) that the OnCE is waiting for commands. After receiving a read command,the DSO pin will be pulsed low to indicate that the requested data is available and theOnCE serial port is ready to receive clocks in order to deliver the data. After receivinga write command, the DSO pin will be pulsed low to indicate that the OnCE serial portis ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided.During hardware reset and when the processor is idle, the DSO pin is held high.2 - 12DSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.Freescale Semiconductor, Inc...PLL PINS2.3.4Debug Request Input (DR)The debug request input (DR) allows the user to enter the debug mode of operation fromthe external command controller.
When DR is asserted, it causes the DSP to finish thecurrent instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the DSI line. While in debug mode,the DR pin lets the user reset the OnCE controller by asserting it and deasserting it afterreceiving an acknowledge. It may be necessary to reset the OnCE controller in caseswhere synchronization between the OnCE controller and external circuitry is lost. Asserting DR when the DSP is in the WAIT or the STOP state, and keeping it asserted until anacknowledge pulse in the DSP is produced, sends the DSP into the debug mode.
Afterreceiving the acknowledge, DR must be deasserted before sending the first OnCE command. For more information, see Section 10.6 METHODS OF ENTERING THE DEBUGMODE in the DSP56000 Family Manual (DSP56KFAMUM/AD).2.4PLL PINSThe following pins are dedicated to the PLL operation:•••••Analog PLL Circuit Power (PVCC) — The Vcc input is dedicated to the analogPLL circuits.
The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the Vcc power rail. PVcc shouldbe bypassed to PGND by a 0.1µF capacitor located as close as possible to thechip package.Analog PLL Circuit Ground (PGND) — This GND input is dedicated to the analog PLL circuits.
The pin should be provided with an extremely low impedancepath to ground. PVcc should be bypassed to PGND by a 0.1µF capacitor located as close as possible to the chip package.CKOUT Power (CLVCC) — This input acts as VCC for the CKOUT output. Thevoltage should be well regulated and the pin should be provided with an extremely low impedance path to the VCC power rail.
CLVCC should be bypassed to CLGND by a 0.1µF capacitor located as close as possible to the chippackage.CKOUT Ground (CLGND) — This input acts as GND for the CKOUT output.The pin should be provided with an extremely low impedance path to ground.CLVCC should be bypassed to CLGND by a 0.1µF capacitor located as closeas possible to the chip package.PLL Filter Capacitor (PCAP) — This input is used to connect an external capacitor needed for the PLL filter. One terminal of the capacitor is connected toPCAP while the other terminal is connected to PVCC.
The capacitor value isspecified in the DSP56002 Technical Data Sheet (DSP56002/D).MOTOROLADSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.com2 - 13Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...TIMER/EVENT COUNTER MODULE PIN•Output Clock (CKOUT) — This output pin provides a 50% duty cycle outputclock synchronized to the internal processor clock when the PLL is enabled andlocked. When the PLL is disabled, the output clock at CKOUT is derived from,and has the same frequency and duty cycle as, EXTAL.Note: If the PLL is enabled and the multiplication factor is less than or equal to4, then CKOUT is synchronized to EXTAL.
(For information on theDSP56002’s PLL multiplication factor, see Section Section 3.6 PLLMULTIPLICATION FACTOR.•CKOUT Polarity Control (CKP) — This input pin defines the polarity of the CKOUT clock output. Strapping CKP through a resistor to GND will make the CKOUT polarity the same as the EXTAL polarity. Strapping CKP through a resistorto Vcc will make the CKOUT polarity the inverse of the EXTAL polarity. The CKOUT clock polarity is internally latched at the end of the hardware reset, so thatany changes of the CKP pin logic state after deassertion of hardware reset willnot affect the CKOUT clock polarity.PLL Initialization Input (PINIT) — During the assertion of hardware reset, thevalue at the PINIT input pin is written into the PEN bit of the PLL control register.The PEN bit enables the PLL by causing it to derive the internal clocks from thePLL VCO output.
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