Сигнальный МП Motorola DSP56002 (1086189), страница 10
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The input and output signals are organized into the functional groupsindicated in Section Figure 2-1. The signals are discussed in the paragraphs that follow.Numberof PinsFunctional GroupPort A Data Bus24Port A Address19Port A Bus Control7Port B Host Interface15Port C Synchronous Comm. Interface3Port C Synchronous Serial Interface6Interrupt and Mode Control4PLL and Clock7On-chip Emulation (OnCE)4Power (VCC)16Ground (GND)24Timer1Reserved2Total (for the PGA package)132D0-D23DGND(6)DVCC(3)A0-A15PSDSX/YAGND(5)AVCC(3)BNRDWRBRBGWTBSCGNDCVCCMODC/NMIMODB/IRQBMODA/IRQARESETEXTALXTALQGND(4)QVCC(4)TIODSP56002Port BHOSTH0-H7HA0-HA2HR/WHENHREQHACKHGND(4)HVCC(2)Port CSCIRXDTXDSCLKPort ADataPort AAddressPort AControlSVCCSGND(2)Port CSSI132 pinsOnCEDSCK/OS1DSI/OS0DSODRPLLPVCCPGNDPCAPCKPPLOCKPINITInterrupt/ModeControlTimerRESERVED (2)SC0-SC2SCKSRDSTDCLVCCCLGNDCKOUTFigure 2-1 DSP56002 Signals2.2.1Port A Address and Data BusThe Port A address and data bus signals control the access to external memory.
They arethree-stated during reset unless noted otherwise, and may require pull-up resistors to minimize power consumption and to prevent erroneous operation.Note: All unused inputs should have pull-up resistors for two reasons: 1) floating inputsdraw excessive power, and 2) a floating input can cause erroneous operation. ForMOTOROLADSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.com2-3Freescale Semiconductor, Inc.SIGNAL DESCRIPTIONSFreescale Semiconductor, Inc...example, during reset, all signals are three-stated. Without pull-up resistors, the BRand WT signals may become active, causing two or more memory chips to try tosimultaneously drive the external bus, which can damage the memory chips.
A pullup resistor in the 50K-ohm range should be sufficient. Also, for future enhancements, all reserved pins (see Section Figure 2-1) should be left unconnected.2.2.1.1Address (A0–A15)These three-state output pins specify the address for external program and data memoryaccesses. To minimize power dissipation, A0–A15 do not change state when externalmemory spaces are not being accessed.2.2.1.2Data Bus (D0–D23)These pins provide the bidirectional data bus for external program and data memory accesses. D0–D23 are in the high-impedance state when the bus grant signal is asserted.2.2.2Port A Bus ControlThe Port A bus control signals are discussed in the following paragraphs.
The bus controlsignals provide a means to connect additional bus masters (which may be additionalDSPs, microprocessors, direct memory access (DMA) controllers, etc.) through port A tothe DSP56002. They are three-stated during reset and may require pull-up resistors toprevent erroneous operation.2.2.2.1Program Memory Select (PS)This three-state output is asserted only when external program memory is referenced(see Table 2-1).Table 2-1 Program and Data Memory Select Encoding2-4PSDSX/YExternal Memory Reference111No Activity101X Data Memory on Data Bus100Y Data Memory on Data Bus011Program Memory on Data Bus (Not Exception)010External Exception Fetch: Vector or Vector +1(Development Mode Only)00XReserved110ReservedDSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SIGNAL DESCRIPTIONS2.2.2.2Data Memory Select (DS)This three-state output is asserted only when external data memory is referenced (see Table 2-1).2.2.2.3X/Y Select (X/Y)This three-state output selects which external data memory space (X or Y) is referencedby DS (see Table 2-1).Freescale Semiconductor, Inc...2.2.2.4Read Enable (RD)This three-state output is asserted to read external memory on the data bus (D0–D23).2.2.2.5Write Enable (WR)This three-state output is asserted to write external memory on the data bus (D0–D23).2.2.2.6Bus Needed (BN)The BN output pin is asserted whenever the chip requires the external memory expansionport (Port A).
During instruction cycles where the external bus is not required, BN is deasserted. If an external device has requested the bus by asserting the BR input and the DSPhas granted the bus (by asserting BG), the DSP will continue processing as long as noexternal accesses are required. If an external access is required and the chip is not thebus master, it will stop processing and remain in wait states until bus ownership is returned. If the BN pin is asserted when the chip is not the bus master, this indicates thatprocessing has stopped and the DSP is waiting to acquire bus ownership. An external arbiter may use this pin to help decide when to return bus ownership to the DSP.Note: The BN pin cannot be used as an early indication of imminent external bus accessbecause it is valid later than the other bus control signal BS.During hardware reset, BN is deasserted.2.2.2.7Bus Request (BR)When the bus request input (BR) is asserted, the DSP56002 will always relinquish the busto an external device such as a processor or DMA controller.
The external device will become the new master of the external address and data buses while the DSP continuesinternal operations using internal memory spaces. When BR is deasserted, theDSP56002 will again assume bus mastership.When BR is asserted, the DSP56002 will always release Port A, including A0–A15, D0–D23, and the bus control pins (PS, DS, X/Y, RD, WR, and BS) by placing them in the highimpedance state, after the execution of the current instruction has been completed.Note: To prevent erroneous operation, the BR pin should be pulled up when it is not in use.MOTOROLADSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.com2-5Freescale Semiconductor, Inc.SIGNAL DESCRIPTIONSFreescale Semiconductor, Inc...2.2.2.8Bus Grant (BG)When this output is asserted, it signals to the external device that it has been granted the external bus (i.e.
Port A has been three-stated).This output is deasserted during hardware reset.2.2.2.9Bus Strobe (BS)The BS output is asserted when the DSP accesses Port A. It acts as an early indicationof the state of the external bus access by the DSP56002. It may also be used with the buswait input, WT, to generate wait states, a feature which provides capabilities such as connecting asynchronous devices to the DSP, allowing devices with differing timingrequirements to reside in the same memory space, allowing a bus arbiter to provide a fastmultiprocessor bus access, and providing an alternative to the WAIT and STOP instructions to halt the DSP at a known program location and have a fast restart.
This output isdeasserted during hardware reset.2.2.2.10Bus Wait (WT)For as long as it is asserted by an external device, this input allows that device to forcethe DSP56002 to generate wait states. If WT is asserted when BS is asserted, wait stateswill be inserted into the current cycle (see the DSP56002 Technical Data Sheet(DSP56002/D) for timing details.2.2.3Interrupt and Mode ControlThe interrupt and mode control pins select the chip’s operating mode as it comes out ofhardware reset, and they receive interrupt requests from external sources.2.2.3.1 Mode Select A/External Interrupt Request A (MODA/IRQA)/STOP RecoveryThis input pin has three functions. It works with the MODB and MODC pins to select thechip’s operating mode, it receives an interrupt request from an external source, and itturns on the internal clock generator, causing the chip to recover from the stop processingstate.
Reset causes this input to act as MODA.During reset, this pin should be forced to the desired state, because as the chip comesout of reset, it reads the states of MODA, MODB, and MODC and writes the informationto the Operating Mode Register to set the chip’s operating mode. (Operating Modes arediscussed in SECTION 3 MEMORY MODULES AND OPERATING MODES.) After thechip has left the reset state, the MODA pin automatically changes to external interruptrequest IRQA.IRQA receives external interrupt requests. It can be programmed to be level sensitive ornegative edge triggered.
When the signal is edge triggered, triggering occurs at a voltagelevel and is not directly related to the fall time of the interrupt signal. However, as the fall2-6DSP56002 PIN DESCRIPTIONSFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SIGNAL DESCRIPTIONStime of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases.Freescale Semiconductor, Inc...2.2.3.2Mode Select B/External Interrupt Request B (MODB/IRQB)This input pin works with the MODA and MODC pins to select the chip’s operating mode,and it receives an interrupt request from an external source.
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