Сигнальный МП Motorola DSP56002 (1086189), страница 14
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Internal Y Data RAM and ROM are Disabled andare part of External Memory3.3.4Chip Operating Mode (Bit 4)The MC bit, together with bits MA and MB, define the program memory map and the operatingmode of the chip. Upon reset, the processor loads this bit from the MODC external mode select pin. After the DSP leaves the reset state, MC can be changed under software control.3.3.5Reserved (Bit 5)This bit is reserved for future expansion and will be read as zero during read operations.3.3.6Stop Delay (Bit 6)The SD bit determines the length of the clock stabilization delay that occurs when theprocessor leaves the stop processing state.
If the stop delay bit is zero when the chipleaves the stop state, a 64K clock cycle delay is selected before continuing the stopinstruction cycle. However, if the stop delay bit is one, the delay before continuing theinstruction cycle is long enough to allow a clock stabilization period for the internal clockto begin oscillating and to stabilize. (See the DSP56002 Technical Data Sheet(DSP56002/D) for the actual timing values.) When a stable external clock is used, theshorter delay allows faster start-up of the DSP.3.3.7Reserved OMR Bits (Bits 7–23)These bits are reserved for future expansion and will be read as zero during read operations.3.4DSP56002 OPERATING MODESThe user can set the chip operating mode through hardware by pulling high the MODC,MODB, and MODA pins appropriately, and then assert the RESET pin.
When the DSPleaves the reset state, it samples the mode pins and writes to the OMR to set the initialoperating mode.MOTOROLAMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.com3-7Freescale Semiconductor, Inc.DSP56002 OPERATING MODESChip operating modes can also be changed using software to write the operating modebits (MC, MB, MA) in the OMR. Changing operating modes does not reset the DSP.Note: The user should disable interrupts immediately before changing the OMR to prevent an interrupt from going to the wrong memory location.
Also, one no-operation(NOP) instruction should be included after changing the OMR to allow for remapping to occur.Freescale Semiconductor, Inc...Table 3-2 DSP56002 Operating Mode SummaryOperatingModeMCMBMA0000Single-Chip Mode - P: RAM enabled, reset @ $00001001Bootstrap from EPROM, exit in Mode 02010Normal Expanded Mode - P: RAM enabled, reset @ $E0003011Development Mode - P: RAM disabled, reset @ $00004100Reserved for Bootstrap5101Bootstrap from Host, exit in Mode 06110Bootstrap from SCI (external clock), exit in Mode 07111Reserved for BootstrapDescription3.4.1Single Chip Mode (Mode 0)In the single-chip mode, all internal program and data RAM memories are enabled (seeFigure 3-1). A hardware reset causes the DSP to jump to internal program memory location $0000 and resume execution. The memory maps for mode 0 and mode 2 (see Figure3-1) are identical.
The difference between the two modes is that reset vectors to programmemory location $0000 in mode 0 and vectors to location $E000 in mode 2.3.4.2Bootstrap From EPROM (Mode 1)The bootstrap modes allow the DSP to load a program from an inexpensive byte-wideROM into internal program memory during a power-on reset. On power-up, the waitstate generator adds 15 wait states to all external memory accesses so that slow memory can be used. The bootstrap program uses the bytes in three consecutive memorylocations in the external ROM to build a single word in internal program memory.3-8MEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.DSP56002 OPERATING MODESIn the bootstrap mode, the chip enables the bootstrap ROM and executes the bootstrapprogram.
(The bootstrap program code is shown in Appendix A.) The bootstrap ROM contains the bootstrap firmware program that performs initial loading of the DSP56002program RAM. Written in DSP56002 assembly language, the program initializes the program RAM by loading from an external byte-wide EPROM starting at location P:$C000.Freescale Semiconductor, Inc...The EPROM is typically connected to the chip’s address and data bus.The data contentsof the EPROM must be organized as shown in Table 3-3 Organization of EPROM DataContents.+5 VDR DSP56002BRHACKWTMODA/IRQAFROM OPENCOLLECTORBUFFER2716MODC/NMIMBD301*PSMBD301*A0-A10FROMRESETFUNCTIONRESETD0-D7CE118A0-A10D0-D7MBD301*FROM OPENCOLLECTORBUFFERMODB/IRQBNotes: 1.
*These diodes must be Schottky diodes.2. All resistors are 15KΩ unless noted otherwise.3. When in RESET, IRQA, IRQB and NMI mustbe deasserted by external peripherals.ADDRESS OF EXTERNALBYTE-WIDE P MEMORYCONTENTS LOADEDTO INTERNAL P: RAM AT:P:$C000P:$C001P:$C002•••P:$C5FDP:$C5FEP:$C5FFP:$0000 LOW BYTEP:$0000 MID BYTEP:$0000 HIGH BYTE•••P:$01FF LOW BYTEP:$01FF MID BYTEP:$01FF HIGH BYTEFigure 3-3 Port A Bootstrap CircuitMOTOROLAMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.com3-9Freescale Semiconductor, Inc.DSP56002 OPERATING MODESTable 3-3 Organization of EPROM Data ContentsFreescale Semiconductor, Inc...Address of ExternalByte-Wide Memory:Contents Loaded to InternalProgram RAM at:P:$C000P:$0000low byteP:$C001P:$0000mid byteP:$C002P:$0000high byte••••••P:$C5FDP:$01FFlow byteP:$C5FEP:$01FFmid byteP:$C5FFP:$01FFhigh byteAfter loading the internal memory, the DSP switches to the single-chip mode (Mode 0) andbegins program execution at on-chip program memory location $0000.If the user selects Mode 1 through hardware (MODA, MODB, MODC pins), the followingactions occur once the processor comes out of the reset state.1.
The control logic maps the bootstrap ROM into the internal DSP program memory space starting at location $0000.2. The control logic causes program reads to come from the bootstrap ROM (onlyaddress bits 5–0 are significant) and all writes go to the program RAM (all address bits are significant). This condition allows the bootstrap program to loadthe user program from $0000–$01FF.3. Program execution begins at location $0000 in the bootstrap ROM. The bootstrap ROM program loads program RAM from the external byte-wide EPROMstarting at P:$C000.4.
The bootstrap ROM program ends the bootstrap operation and begins executingthe user program. The processor enters Mode 0 by writing to the OMR. This action is timed to remove the bootstrap ROM from the program memory map andre-enable read/write access to the program RAM. The change to Mode 0 istimed to allow the bootstrap program to execute a single-cycle instruction (clearstatus register), then a JMP #<00, and begin execution of the user program atlocation $0000.3 - 10MEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.DSP56002 OPERATING MODESThe user can also get into the bootstrap mode (Mode 1) through software by writing zeroto MC and MB, and one to MA in the OMR.
This selection initiates a timed operation tomap the bootstrap ROM into the program address space (after a delay to allow executionof a single-cycle instruction), and then a JMP #<00 to begin the bootstrap process described previously in steps 1 through 4. This technique allows the user to reboot thesystem (with a different program, if desired).Freescale Semiconductor, Inc...The code to enter the bootstrap mode is as follows:MOVEP#0,X:$FFFF;Disable interrupts.MOVEC#1,OMR;The bootstrap ROM is mapped;into the lowest 64 locations;in program memory.NOPJMP;Allow one cycle delay for the;remapping.<$0;Begin bootstrap.The code disables interrupts before executing the bootstrap code. Otherwise, an interruptcould cause the DSP to execute the bootstrap code out of sequence because the bootstrap program overlays the interrupt vectors.3.4.3Normal Expanded Mode (Mode 2)In this mode, the internal program RAM is enabled and the hardware reset vectors to location $E000.
(The memory maps for Mode 0 and Mode 2 are identical. The differencefor Mode 0 is that, after reset, the instruction at location $E000 is executed instead of theinstruction at $0000 — see Figure 3-1 and Table 3-2).3.4.4Development Mode (Mode 3)In this mode, the internal program RAM is disabled and the hardware reset vectors to location $0000. All references to program memory space are directed to external programmemory. The reset vector points to location $0000. The memory map for this mode isshown in Figure 3-1 and Table 3-2.3.4.5Reserved (Mode 4)This mode is reserved for future definition. If selected, it defaults to Mode 5.3.4.6Bootstrap From Host (Mode 5)In this mode, the Bootstrap ROM is enabled and the bootstrap program is executed.
This issimilar to Mode 1 except that the bootstrap program loads internal P: RAM from the Host Port.MOTOROLAMEMORY MODULES AND OPERATING MODESFor More Information On This Product,Go to: www.freescale.com3 - 11Freescale Semiconductor, Inc.DSP56002 INTERRUPT PRIORITY REGISTERFreescale Semiconductor, Inc...Note: The difference between Modes 1 and 5 in the DSP56002 and Mode 1 in theDSP56001 may be considered software incompatibility.
A DSP56001 program thatreloads the internal P: RAM from the Host Port by setting MB-MA = 01 (assumingexternal pull-up resistor on bit 23 of P:$C000) will not work correctly in theDSP56002. In the DSP56002, the program would trigger a bootstrap from the external EPROM.
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