Сигнальный МП Motorola DSP56002 (1086189), страница 20
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Normally, it is not goodprogramming practice to activate a peripheral before programming it. However, reset activates the Port B general-purpose I/O as all inputs; the alternative is to configure Port B asan HI, which may not be desirable. In this case, it is probably better to insure that Port Bis initially configured for general-purpose I/O, and then configure the data direction anddata registers. It may be better in some situations to program the data direction or the dataregisters first to prevent two devices from driving one signal. The order of steps 1, 2, and3 in Figure 5-7 is optional and can be changed as needed.5.2.2Port B General Purpose I/O TimingGeneral purpose data written to Port B is synchronized to the central processing unit(CPU) but delayed by one instruction cycle.
For example, the instructionMOVEDATA15,X:PORTBDATA24,Y:EXTERN1. writes 15 bits of data to the Port B register, but the output pins do not changeuntil the following instruction cycle2. writes 24 bits of data to the external Y memory, which appears on Port A during T2 and T3 of the current instructionAs a result, if it is desirable to synchronize Port A and Port B outputs, two instructions mustbe used:MOVENOPDATA15,X:PORTBDATA24,Y:EXTERNThe NOP can be replaced by any instruction that allows parallel moves.
Inserting one ormore “MOVE DATA15,X:PORTB DATA24,Y:EXTERN” instructions between the first and5-8PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.GENERAL PURPOSE I/O CONFIGURATIONsecond instruction effectively produces an external 39-bit write each instruction cycle withonly one instruction cycle lost in setup time:Freescale Semiconductor, Inc...MOVEMOVEMOVE::MOVENOPDATA15,X:PORTBDATA15,X:PORTBDATA15,X:PORTBDATA15,X:PORTBDATA24,Y:EXTERNDATA24,Y:EXTERNDATA24,Y:EXTERNDATA24,Y:EXTERNOne application of this technique is to create an extended address for Port A by concatenating the Port A address bits (instead of data bits) to the Port B general-purpose outputbits.
The Port B general-purpose I/O register would then work as a base address register,allowing the address space to be extended from 64K words (16 bits) to two billion words(16 bits +15 bits = 31 bits).STEP 1. ACITIVATE PORT B FOR GENERAL - PURPOSE I/O:SET BITS 0 AND 1 TO ZERO15X:$FFE00* * * *** * ** * * * **BC BC PORT B10 CONTROL REGISTER (PBC)STEP 2. SET INDIVIDUAL PINS TO INPUT OR OUTPUT:BDxx = 0INPUTORBDxx = 1OUTPUT15X:$FFE2*0BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD PORT B DATA DIRECTION14 13 12 11 10 9876543210 REGISTER (PBDDR)STEP 3.
WRITE OR READ DATA:PBxxINPUT IF BDxx = 0ORPBxxOUTPUT IF BDxx = 115X:$FFE4*0PB14PB PB PB PB PB PB PB PB PB PB PB PB PB PB PORT B DATA13 12 11 10 9876543210 REGISTER (PBD)*Reserved; write as zero.Figure 5-7 I/O Port B ConfigurationMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5-9Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...Port B uses the DSP CPU four-phase clock for its operation.
Therefore, if wait states areinserted in the DSP CPU timing, they also affect Port B timing. The result is that ports Aand B in the previous synchronization example will always stay synchronized, regardlessof how many wait states are used.5.3HOST INTERFACE (HI)The HI is a byte-wide, full-duplex, double-buffered, parallel port which may be connecteddirectly to the data bus of a host processor.
The host processor may be any of a numberof industry standard microcomputers or microprocessors, another DSP, or DMA hardwarebecause this interface looks like static memory. The HI is asynchronous and consists oftwo banks of registers – one bank accessible to the host processor and a second bankaccessible to the DSP CPU (see Figure 5-8). A brief description of the HI features is presented in the following listing:Speed3.3 Million Word/Sec Interrupt Driven Data Transfer Rate (This is the maximum interruptrate for the DSP56002 running at 40 MHz – i.e., one interrupt every six instruction cycles.)Signals (15 Pins)H0–H7Host Data BusHA0-HA2Host Address SelectHR/WHost Read/Write ControlHost Transfer EnableHENHost RequestHREQHost AcknowledgeHACKInterface – DSP CPU SideMapping: Three X: Memory LocationsData Word: 24 BitsTransfer Modes:DSP to HostHost to DSPHost CommandHandshaking Protocols:Software PolledInterrupt Driven (Fast or Long Interrupts)Direct Memory AccessInstructions:Memory-mapped registers allow the standard MOVE instruction to be usedSpecial MOVEP instruction provides for I/O service capability using fast interruptsBit addressing instructions (BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET,JSSET) simplify I/O service routinesI/O short addressing provides faster execution with fewer instruction words5 - 10PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Interface – Host SideMapping:Eight Consecutive Memory LocationsMemory-Mapped Peripheral for Microprocessors, DMA Controllers, etc.Freescale Semiconductor, Inc...Data Word: Eight BitsTransfer Modes:DSP to HostHost to DSPHost CommandMixed 8-, 16-, and 24-Bit Data TransfersHandshaking Protocols:Software PolledInterrupt Driven and Compatible with MC68000Cycle Stealing DMA with InitializationDedicated Interrupts:Separate Interrupt Vectors for Each Interrupt SourceSpecial host commands force DSP CPU interrupts under host processor control,which are useful for:Real-Time Production DiagnosticsDebugging Window for Program DevelopmentHost Control Protocols and DMA SetupFigure 5-8 is a block diagram showing the registers in the HI.
These registers can bedivided vertically down the middle into registers visible to the host processor on the leftand registers visible to the DSP on the right. They can also be divided horizontally intocontrol at the top, DSP-to-host data transfer in the middle (HTX, RXH, RXM, and RXL),and host-to-DSP data transfer at the bottom (THX, TXM, TXL, and HRX).5.3.1Host Interface – DSP CPU ViewpointThe DSP CPU views the HI as a memory-mapped peripheral occupying three 24-bitwords in data memory space. The DSP may use the HI as a normal memory-mappedperipheral, using either standard polled or interrupt programming techniques. Separatetransmit and receive data registers are double buffered to allow the DSP and host processor to efficiently transfer data at high speed.
Memory mapping allows DSP CPUcommunication with the HI registers to be accomplished using standard instructions andaddressing modes. In addition, the MOVEP instruction allows HI-to-memory and memoryto-HI data transfers without going through an intermediate register. Both hardware andsoftware reset disable the HI and change Port B to general-purpose I/O with all pins designated as inputs.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 11Freescale Semiconductor, Inc.HOST INTERFACE (HI)X:$FFE8INTERRUPT CONTROLREGISTER(READ/WRITE)$0ICRDSP CPU GLOBALDATA BUSHCRHOST CONTROL REGISTER(READ/WRITE)X:$FFE9Freescale Semiconductor, Inc...$1CVR$2ISRCOMMAND VECTORREGISTER(READ/WRITE)HSRINTERRUPT STATUSREGISTER(READ ONLY)CONTROLHOST STATUS REGISTER(READ ONLY)LOGICHOST MPUDATA BUSH0 - H7$3IVRINTERRUPT VECTORREGISTER(READ/WRITE)$5RXHRECEIVE BYTEREGISTERS(READ ONLY)8$6RXMX:$FFEB24HTXHOST TRANSMITDATA REGISTER(WRITE ONLY)$7RXLX:$FFEB$5TXH$6TXM24TRANSMIT BYTEREGISTERS(WRITE ONLY)24HRXHOST RECIEVEDATA REGISTER(READ ONLY)$7TXLFigure 5-8 HI Block Diagram5.3.2Programming Model – DSP CPU ViewpointThe HI has two programming models: one for the DSP programmer and one for the host processor programmer.
In most cases, the notation used reflects the DSP perspective. The HI –DSP programming model is shown in Figure 5-9. There are three registers: a control register(HCR), a status register (HSR), and a data transmit/receive register (HTX/HRX). These registers can only be accessed by the DSP56002; they can not be accessed by the hostprocessor. The HI host processor programming model is shown in Figure 5-12.5 - 12PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)DSP CPU HI FLAGSHOST FLAG 3HOST FLAG 2700X:$FFE800HF3(0)HF2(0)HCIE(0)HTIE(0)HRIE(0)HOST CONTROL REGISTER (HCR)(READ/WRITE)Freescale Semiconductor, Inc...INTERRUPT ENABLESHOST RECEIVEHOST TRANSMITHOST COMMANDHOST HI FLAGSHOST FLAG 1HOST FLAG 07X:$FFE90DMA(0)00HF1(0)HF0(0)HCP(0)HTDE HRDF HOST STATUS REGISTER (HSR)(READ ONLY)(1)(0)HOST RECEIVE DATA FULLHOST TRANSMIT DATA EMPTYHOST COMMAND PENDING2316 158 70X:$FFEBRECEIVE HIGH BYTERECEIVE MIDDLE BYTERECEIVE LOW BYTEX:$FFEBTRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE70 70 7HOST RECEIVE DATA REGISTER(HRX) (READ ONLY)HOST TRANSMIT DATA REGISTER(HTX) (WRITE ONLY)0NOTE: The numbers in parentheses are reset values.Figure 5-9 Host Interface Programming Model – DSP ViewpointThe following paragraphs describe the purpose and operation of each bit in each registerMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 13Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...of the HI visible to the DSP CPU.
The effects of the different types of reset on these registers are shown. A brief discussion of interrupts and operation of the DSP side of the HIcomplete the programming model from the DSP viewpoint. The programming model fromthe host viewpoint begins at Section 5.3.3.1 Programming Model – Host ProcessorViewpoint.5.3.2.1Host Control Register (HCR)The HCR is an 8-bit read/write control register used by the DSP to control the HI interruptsand flags. The HCR cannot be accessed by the host processor.
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