Сигнальный МП Motorola DSP56002 (1086189), страница 22
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The DSPCPU interrupts are internal and do not require the use of an external interrupt pin (see Figure 5-11). When the appropriate mask bit in the HCR is set, an interrupt condition causedby the host processor sets the appropriate bit in the HSR, which generates an interruptrequest to the DSP CPU. The DSP acknowledges interrupts caused by the host processorby jumping to the appropriate interrupt service routine. The three possible interrupts are1) receive data register full, 2) transmit data register empty, and 3) host command. Thehost command can access any interrupt vector in the interrupt vector table although it hasa set of vectors reserved for host command use. The DSP interrupt service routine mustread or write the appropriate HI register (clearing HRDF or HTDE, for example) to clearthe interrupt.
In the case of host command interrupts, the interrupt acknowledge from theprogram controller will clear the pending interrupt condition.5.3.2.7Host Port Usage Considerations – DSP SideSynchronization is a common problem when two asynchronous systems are connected,and careful synchronization is required when reading multi-bit registers that are written byanother asynchronous system. The considerations for proper operation on the DSP CPUside are discussed in the following paragraphs, and considerations for the host processor5 - 18PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)MASK700X:$FFE00HF3HF2HCIEHTIEHCRHRIEDSP CPU INTERRUPTSRECIEVE DATA FULLP:$0020Freescale Semiconductor, Inc...TRANSMIT DATA EMPTYP:$0022HOST COMMANDP:(2xHV ➞ $0000 - $007E)RESET ➞ HV = $0012 in CVR7X:$FFE0DMA00HF1HF2HCPHTDEHRDFHCRSTATUSFigure 5-11 HSR–HCR Operationside are discussed in Section 5.3.6.5 Host Port Usage Considerations – Host Side.DMA, HF1, HF0, HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface.
These bits are individually synchronized to the DSP clock.The only system problem with reading status occurs if HF1 and HF0 are encoded as apair because each of their four combinations (00, 01, 10, and 11) has significance. Thereis a small possibility that the DSP will read the status bits during the transition and receive“01” or “10” instead of “11”. The solution to this potential problem is to read the bits twicefor consensus (See Section 5.3.6.5 Host Port Usage Considerations – Host Side foradditional information).5.3.3Host Interface – Host Processor ViewpointThe HI appears to the host processor as eight words of byte-wide static memory. The hostmay access the HI asynchronously by using polling techniques or interrupt-based techniques.
Separate transmit and receive data registers are double buffered to allow the DSPCPU and host processor to transfer data efficiently at high speed. The HI contains a rudimentary DMA controller, which makes generating addresses (HA0–HA2) for the TX/RXMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 19Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...registers in the HI unnecessary.5.3.3.1Programming Model – Host Processor ViewpointThe HI appears to the host processor as a memory-mapped peripheral occupying eightbytes in the host processor address space (see Figure 5-12 and Figure 5-13).
These registers can be viewed as one control register (ICR), one status register (ISR), three dataregisters (RXH/TXH, RXM/TXM, and RXL/TXL), and two vector registers (IVR and CVR).The CVR is a special command register that is used by the host processor to issue commands to the DSP.
These registers can be accessed only by the host processor; theycan not be accessed by the DSP CPU. Host processors may use standard host processor instructions (e.g., byte move) and addressing modes to communicate with the HIregisters.
The HI registers are addressed so that 8-bit MC6801-type host processors canuse 16-bit load (LDD) and store (STD) instructions for data transfers. The 16-bitMC68000/MC68010 host processor can address the HI using the special MOVEPinstruction for word (16-bit) or long-word (32-bit) transfers. The 32-bit MC68020 host processor can use its dynamic bus sizing feature to address the HI using standard MOVEword (16-bit), long-word (32-bit) or quad-word (64-bit) instructions.
The HREQ andHACK handshake flags are provided for polled or interrupt-driven data transfers with thehost processor. Because the DSP interrupt response is sufficiently fast, most host microprocessors can load or store data at their maximum programmed I/O (non-DMA)instruction rate without testing the handshake flags for each transfer. If the full handshake is not needed, the host processor can treat the DSP as fast memory, and data canbe transferred between the host processor and the DSP at the fastest host processordata rate.
DMA hardware may be used with the handshake flags to transfer data withouthost processor intervention.One of the most innovative features of the host interface is the host command feature.With this feature, the host processor can issue vectored exception requests to theDSP56002. The host may select any one of 64 DSP56002 exception routines to be executed by writing a vector address register in the HI. This flexibility allows the hostprogrammer to execute up to 64 preprogrammed functions inside the DSP56002. Forexample, host exceptions can allow the host processor to read or write DSP56002 registers (X, Y, or program memory locations), force exception handlers (e.g., SSI, SCI, IRQA,IRQB exception routines), and perform control and debugging operations if exception routines are implemented in the DSP56002 to perform these tasks.5.3.3.2Interrupt Control Register (ICR)The ICR is an 8-bit read/write control register used by the host processor to control the HIinterrupts and flags.
ICR cannot be accessed by the DSP CPU. ICR is a read/write regis-5 - 20PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)MODESFLAGS7INIT(0)$0Freescale Semiconductor, Inc...0HM1(0)HM0(0)00Interrupt Mode (DMA Off)0124-Bit DMA Mode1016-Bit DMA Mode118-Bit DMA Mode7HF0(0)TREQ RREQ(0)(0)05HC(0)$1HF1(0)0HOST VECTOR($12)0FLAGSCOMMAND VECTOR REGISTER (CVR)(READ/WRITE)STATUS7$2HREQ(0)INTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)0DMA(0)0HF3(0)HF2(0)TRDY TXDE RXDF(1)(1)(0)7INTERRUPT STATUS REGISTER (ISR)(READ ONLY)0INTERRUPT VECTOR NUMBER($0F)$3INTERRUPT VECTOR REGISTER (IVR)(READ/WRITE)RECEIVE BYTE REGISTERS (RXH:RXM:RXL)(READ ONLY)31$424 23$516 15$68 7$700000000RXHRECEIVE HIGH BYTERXMRECEIVE MIDDLE BYTERXLRECEIVE LOW BYTENOT USEDTXHTRANSMIT HIGH BYTETXMTRANSMIT MIDDLE BYTETXLTRANSMIT LOW BYTE707070 700TRANSMIT BYTE REGISTERS (TXH:TXM:TXL)(WRITE ONLY)NOTE: The numbers in parentheses are reset values.Figure 5-12 Host Processor Programming Model – Host Sideter, which allows the use of bit manipulation instructions on control register bits.
TheMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 21Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...HOST ADDRESSHA0 - HA2$0ICRINTERRUPT CONTROL$1CVRCOMMAND VECTOR$2ISRINTERRUPT STATUS$3IVRINTERRUPT VECTOR$400000000$5RXH/TXH$6RXM/TXM$7RXL/TXLUNUSEDRECEIVE/TRANSMITBYTESHOST DATA BUSH0 - H7Figure 5-13 HI Register Mapcontrol bits are described in the following paragraphs.5.3.3.2.1ICR Receive Request Enable (RREQ) Bit 0The RREQ bit is used to control the HREQ pin for host receive data transfers.In interrupt mode (DMA off), RREQ is used to enable interrupt requests via the externalhost request (HREQ) pin when the receive data register full (RXDF) status bit in the ISRis set. When RREQ is cleared, RXDF interrupts are disabled.
When RREQ is set, theexternal HREQ pin will be asserted if RXDF is set.In DMA modes, RREQ must be set or cleared by software to select the direction of DMAtransfers. Setting RREQ sets the direction of DMA transfer to be DSP to host and enablesthe HREQ pin to request data transfer. Hardware, software, individual, and STOP resetsclear RREQ.5.3.3.2.2ICR Transmit Request Enable (TREQ) Bit 1The TREQ bit is used to control the HREQ pin for host transmit data transfers.In interrupt mode (DMA off), TREQ is used to enable interrupt requests via the externalHREQ pin when the transmit data register empty (TXDE) status bit in the ISR is set.
WhenTREQ is cleared, TXDE interrupts are disabled. When TREQ is set, the external HREQpin will be asserted if TXDE is set.In DMA modes, TREQ must be set or cleared by software to select the direction of DMAtransfers. Setting TREQ sets the direction of DMA transfer to be host to DSP and enablesthe HREQ pin to request data transfer. Hardware, software, individual, and STOP resetsclear TREQ.5 - 22PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Table 5-2 HREQ Pin DefinitionTREQRREQHREQ PinFreescale Semiconductor, Inc...Interrupt Mode00No Interrupts (Polling)01RXDF Request (Interrupt)10TXDE Request (Interrupt)11RXDF and TXDE Request (Interrupts)DMA Mode00No DMA01DSP to Host Request (RX)10Host to DSP Request (TX)11Undefined (Illegal)Table 5-2 summarizes the effect of RREQ and TREQ on the HREQ pin.5.3.3.2.3ICR Reserved Bit (Bit 2)This bit, which is reserved and unused, reads as a logic zero.5.3.3.2.4ICR Host Flag 0 (HF0) Bit 3The HF0 bit is used as a general-purpose flag for host-to-DSP communication.
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