Сигнальный МП Motorola DSP56002 (1086189), страница 24
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The host can writeHC and HV in the same write cycle if desired. Hardware, software, individual, and STOPresets clear HC.5.3.3.4Interrupt Status Register (ISR)The ISR is an 8-bit read-only status register used by the host processor to interrogate thestatus and flags of the HI.
The host processor can write this address without affecting theinternal state of the HI, which is useful if the user desires to access all of the HI registersby stepping through the HI addresses. The ISR can not be accessed by the DSP. The status bits are described in the following paragraphs.5.3.3.4.1ISR Receive Data Register Full (RXDF) Bit 0The RXDF bit indicates that the receive byte registers (RXH, RXM, and RXL) containdata from the DSP CPU and may be read by the host processor. RXDF is set when theHTX is transferred to the receive byte registers.
RXDF is cleared when the receive datalow (RXL) register is read by the host processor. RXL is normally the last byte of thereceive byte registers to be read by the host processor. RXDF can be cleared by the hostprocessor using the initialize function. RXDF may be used to assert the external HREQpin if the RREQ bit is set. Regardless of whether the RXDF interrupt is enabled, RXDF5 - 28PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...provides valid status so that polling techniques may be used by the host processor.Hardware, software, individual, and STOP resets clear RXDF.5.3.3.4.2ISR Transmit Data Register Empty (TXDE) Bit 1The TXDE bit indicates that the transmit byte registers (TXH, TXM, and TXL) are emptyand can be written by the host processor.
TXDE is set when the transmit byte registersare transferred to the HRX register. TXDE is cleared when the transmit byte low (TXL)register is written by the host processor. TXL is normally the last byte of the transmit byteregisters to be written by the host processor. TXDE can be set by the host processorusing the initialize feature. TXDE may be used to assert the external HREQ pin if theTREQ bit is set.
Regardless of whether the TXDE interrupt is enabled, TXDE providesvalid status so that polling techniques may be used by the host processor. Hardware,software, individual, and STOP resets set TXDE.5.3.3.4.3ISR Transmitter Ready (TRDY) Bit 2The TRDY status bit indicates that both the TXH,TXM,TXL and the HRX registers are empty.TRDY=TXDE • HRDFWhen TRDY is set to one, the data that the host processor writes to TXH,TXM, and TXLwill be immediately transferred to the DSP CPU side of the HI. This has many applications. For example, if the host processor issues a host command which causes the DSPCPU to read the HRX, the host processor can be guaranteed that the data it just transferred to the HI is what is being received by the DSP CPU.Hardware, software, individual, and STOP resets set TRDY.5.3.3.4.4ISR Host Flag 2 (HF2) Bit 3The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the CPU side.
HF2can only be changed by the DSP (see Figure 5-10). HF2 is cleared by a hardware orsoftware reset.5.3.3.4.5ISR Host Flag 3 (HF3) Bit 4The HF3 bit in the ISR indicates the state of host flag 3 in the HCR on the CPU side. HF3can only be changed by the DSP (see Figure 5-10). HF3 is cleared by a hardware orsoftware reset.5.3.3.4.6ISR Reserved Bit (Bit 5)This status bit is reserved for future expansion and will read as zero during host processor read operations.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 29Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...5.3.3.4.7ISR DMA Status (DMA) Bit 6The DMA status bit indicates that the host processor has enabled the DMA mode of theHI (HM1 or HM0=1).
When the DMA status bit is clear, it indicates that the DMA mode isdisabled (HM0=HM1=0) and no DMA operations are pending. When DMA is set, it indicates that the DMA mode is enabled and the host processor should not use the activeDMA channel (RXH, RXM, RXL or TXH, TXM, TXL depending on DMA direction) to avoidconflicts with the DMA data transfers.
The channel not in use can be used for polled operation by the host and operates in the interrupt mode for internal DSP exceptions or polling. Hardware, software, individual, and STOP resets clear the DMA status bit.5.3.3.4.8ISR Host Request (HREQ) Bit 7The HREQ bit indicates the status of the external host request output pin (HREQ). Whenthe HREQ status bit is cleared, it indicates that the external HREQ pin is deasserted andno host processor interrupts or DMA transfers are being requested. When the HREQ status bit is set, it indicates that the external HREQ pin is asserted, indicating that the DSPis interrupting the host processor or that a DMA transfer request is occurring.
The HREQinterrupt request may originate from either or both of two sources – the receive byte registers are full or the transmit byte registers are empty. These conditions are indicated bythe ISR RXDF and TXDE status bits, respectively. If the interrupt source has beenenabled by the associated request enable bit in the ICR, HREQ will be set if one or moreof the two enabled interrupt sources is set. Hardware, software, individual, and STOPresets clear HREQ.5.3.3.5Interrupt Vector Register (IVR)The IVR is an 8-bit read/write register which typically contains the exception vector number used with MC68000 Family processor vectored interrupts.
Only the host processorcan read and write this register. The contents of IVR are placed on the host data bus(H0–H7) when both the HREQ and HACK pins are asserted and the DMA mode is disabled. The contents of this register are initialized to $0F by a hardware or software reset,which corresponds to the uninitialized exception vector in the MC68000 Family.5.3.3.6Receive Byte Registers (RXH, RXM, RXL)The receive byte registers are viewed as three 8-bit read-only registers by the host processor. These registers are called receive high (RXH), receive middle (RXM), and receivelow (RXL). These three registers receive data from the high byte, middle byte, and lowbyte, respectively, of the HTX register and are selected by three external host addressinputs (HA2, HA1, and HA0) during a host processor read operation or by an on-chipaddress counter in DMA operations.
The receive byte registers (at least RXL) containvalid data when the receive data register full (RXDF) bit is set. The host processor may5 - 30PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...program the RREQ bit to assert the external HREQ pin when RXDF is set. This informsthe host processor or DMA controller that the receive byte registers are full. These registers may be read in any order to transfer 8-, 16-, or 24-bit data. However, reading RXLclears the receive data full RXDF bit. Because reading RXL clears the RXDF status bit, itis normally the last register read during a 16- or 24-bit data transfer.
Reset does not affectRXH, RXM, or RXL.5.3.3.7Transmit Byte Registers (TXH, TXM, TXL)The transmit byte registers are viewed as three 8-bit write-only registers by the host processor. These registers are called transmit high (TXH), transmit middle (TXM), andtransmit low (TXL). These three registers send data to the high byte, middle byte and lowbyte, respectively, of the HRX register and are selected by three external host addressinputs (HA2, HA1, and HA0) during a host processor write operation. Data may be writteninto the transmit byte registers when the transmit data register empty (TXDE) bit is set.The host processor may program the TREQ bit to assert the external HREQ pin whenTXDE is set. This informs the host processor or DMA controller that the transmit byte registers are empty.
These registers may be written in any order to transfer 8-, 16-, or 24-bitdata. However, writing TXL clears the TXDE bit. Because writing the TXL register clearsthe TXDE status bit, TXL is normally the last register written during a 16- or 24-bit datatransfer. The transmit byte registers are transferred as 24-bit data to the HRX registerwhen both TXDE and the HRDF bit are cleared. This transfer operation sets TXDE andHRDF.
Reset does not affect TXH, TXM, or TXL.5.3.3.8Registers After ResetTable 5-5 shows the result of four kinds of reset on bits in each of the HI registers seenby the host processor. The hardware reset is caused by asserting the RESET pin; thesoftware reset is caused by executing the RESET instruction; the individual reset iscaused by clearing the PBC register bit 0; and the stop reset is caused by executing theSTOP instruction.5.3.4Host Interface PinsThe 15 HI pins are described here for convenience. Additional information, including timing, is given in the DSP56002 Technical Data Sheet (DSP56002/D).5.3.4.1Host Data Bus(H0-H7)This bidirectional data bus transfers data between the host processor and the DSP56002.It acts as an input unless HEN is asserted and HR/W is high, making H0–H7 become outputs and allowing the host processor to read DSP56002 data.
It is high impedance whenHEN is deasserted. H0–H7 can be programmed as general-purpose I/O pins (PB0–PB7)MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 31Freescale Semiconductor, Inc.HOST INTERFACE (HI)when the host interface is not being used. These pins are configured as GPIO input pinsduring hardware reset.5.3.4.2Host Address (HA0–HA2)These inputs provide the address selection for each host interface register. HA0–HA2 canbe programmed as general-purpose I/O pins (PB8–PB10) when the host interface is notbeing used. These pins are configured as GPIO input pins during hardware reset.Freescale Semiconductor, Inc...Table 5-5 Host Registers after Reset (Host Side)Reset TypeRegisterNameICRRegisterDataHWResetSWResetIRResetSTResetINIT0000HM (1 - 0)0000TREQ0000RREQ0000HF (1 - 0)0000HC0000$12$12$12$12HREQ0000DMA0000HF (3 - 2)00——TRDY1111TXDE1111RXDF0000$0F$0F——RXH (23 - 16)————RXM (15 - 8)————RXL (7 - 0)————TXH (23 - 21)————TXM (15 - 8)————TXL (7 - 0)————CVRHV (5 - 0)ISRIVRRXTX5 - 32IV (7 - 0)PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...5.3.4.3Host Read/Write (HR/W)This input selects the direction of data transfer for each host processor access.
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