Сигнальный МП Motorola DSP56002 (1086189), страница 28
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Data is written by thehost processor in a pattern of four bytes, with the high byte being a dummy and the lowbyte being the low byte of the DSP word (see Figure 5-29 and Figure 5-30). Figure 5-30shows how an 8-,16-, 24-, or 32-bit word in the host processor maps into the HI registers.The HI register at address $4 is not used and will read as zero. It is not necessary to useaddress $4, but since many host processors are 16- or 32-bit processors, address $4 willoften be used as part of the 16- or 32-bit word. The low order byte (at $7) should alwaysbe written last since writing to it causes the HI to initiate the transfer of the word to theHRX.
Data is then transferred from the HRX to the DSP program memory. If the hostprocessor needs to terminate the bootstrap loading before 512 words have been downloaded, it can set the HF0 bit in the ICR. The DSP will then terminate the down load andstart executing at location P:$0000. Since the DSP56002 is typically faster than the hostprocessor, hand shaking during the data transfer is normally not required.The actual code used in the bootstrap program is given in APPENDIX A.
The portion ofthe code that loads from the HI is shown in Figure 5-31. The BSET instruction configuresHOSTTRANSMIT/RECEIVEBYTE REGISTERS731HOSTDATA24 23READ - 00000000WRITE - XXXXXXXX16 15HIGHHOST BYTEADDRESS0000000004TXH/RXHHIGH BYTE5TXM/RXMMIDDLE BYTE6TXL/RXLLOW BYTE78 7ACCESS TOLOW BYTEINITIATESTRANSFER0MIDDLELOW8-BIT TRANSFER16-BIT TRANSFER24-BIT TRANSFER32-BIT TRANSFER, LS 24 BITS ARE SIGNIFICANTNOTE: Access low byte lastFigure 5-30 Transmit/Receive Byte RegistersMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 51Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...;**************************************************; This routine loads from the Host Interface.; MC:MB:MA=100 - reserved; MC:MB:MA=101 - Host;*************************************************HOSTLDBSET#0,X:PBCDO#512,_LOOP3_LBLAJCLR#3,X:HSR,_LBLBENDDOJMP<_LOOP3_LBLBJCLR#0,X:HSR,_LBLAMOVEPX:HRX,P:(R0)+JMP<FINISH_LOOP3;Configure Port B as Host;Load 512 instruction words;If HF0=1, stop loading data.;Must terminate the DO loop;;Wait for HRDF to go high;(meaning data is present).;Store 24-bit data in P memory;and go get another 24-bit word.;finish bootstrapFigure 5-31 Bootstrap Code FragmentPort B as the HI and the first JCLR looks for a flag (HF0) to indicate an early terminationof the download.
The second JCLR instruction causes the DSP to wait for a completeword to be received and then a MOVEP moves the data from the HI to memory.5.3.6.2.4DSP to Host Data TransferData is transferred from the DSP to the host processor in a similar manner as from thehost processor to the DSP. Figure 5-32 shows the bits in the status registers (ISR andHSR) and control registers (ICR and HCR) used by the host processor and DSP CPU,respectively. The DSP CPU (see Figure 5-33) can poll the HTDE bit in the HSR (1) tosee when it can send data to the host, or it can use interrupts enabled by the HTIE bit inthe HCR (2). If HTIE=1 and interrupts are enabled, exception processing begins at interrupt vector P:$0022 (3).
The interrupt routine should write data to the HTX (4), which willclear HTDE in the HSR. From the host’s viewpoint, (5) reading the RXL clears RXDF inthe ISR. When RXDF=0 and HTDE=0 (6) the contents of the HTX will be transferred tothe receive byte registers (RXH:RXM:RXL). This transfer sets RXDF in the ISR (7),which the host processor can poll to see if data is available or, if the RREQ bit in the ICRis set, the HI will interrupt the host processor with HREQ (8).The code shown in Figure 5-34 is essentially the same as the MAIN PROGRAM in Figure5-25 except that, since this code will transmit instead of receive data, the HTIE bit is setin the HCR instead of the HRIE bit.The transmit routine used by the code in Figure 5-34 is shown in Figure 5-35.
The interruptvector contains a JSR, which makes it a long interrupt. The code sends a fixed test pattern5 - 52PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLAHREQDMA0HF3HF2TRDYTXDE RXDF0For More Information On This Product,Go to: www.freescale.comPORT BINITHM1HM0HF1HF00TREQ RREQ0INTERRUPTCONTROLREGISTER (HCR)(READ/WRITE)DMA700HF1HF0HCP000HF3HF2Figure 5-32 Bits Used for DSP to Host TransferHTIE — HOST TRANSMIT INTERRUPT ENABLE1 = ENABLE THE DSP INTERRUPT TO P:$0022.0 = DISABLE THE DSP INTERRUPT TO P:$0022.DSP INTERRUPT IS CAUSED BY HTDE = 1X:$FFE87HCIE0HTIEHRIE0HTDE HRDFDSP56002HTDE — HOST TRANSMIT DATA EMPTY1 = HTX IS EMPTY AND CAN BE WRITTEN BY DSP.0 = HTX IS FULL.INTERRUPT STATUSREGISTER (ISR)X:$FFE9(READ ONLY)RREQ —RECEIVE REQUEST ENABLE (USED TO CONTROL THE HREQ PIN)1 = ENABLE INTERRUPT REQUESTS CREATED BY RXDF.0 = DISABLE INTERRUPT REQUESTS.$07MODESRXDF — RECEIVE DATA REGISTER FULL1 = INDICATES THE RECIEVE BYTE REGISTERS (RXH, RXM, RXL)CONTAIN DATA FROM THE DSP.0 = CLEARED BY READING RXL.$27HOSTFreescale Semiconductor, Inc...HOST CONTROLREGISTER (HCR)(READ/WRITE)HOST STATUSREGISTER (HSR)(READ ONLY)Freescale Semiconductor, Inc.HOST INTERFACE (HI)($123456) and then resets the HI for the next interrupt.5 - 535 - 54$7RECEIVE BYTEREGISTERS (RBR)RXL$60For More Information On This Product,Go to: www.freescale.comPORT BINIT7HREQHM1DMAHM00HF1HF3TXDE0TREQRXDFRECEIVEDATA FULLTRDYRREQRECEIVEREQUEST ENABLEHF0HF211HREQPIN00INTERRUPTCONTROLREGISTER (ICR)INTERRUPTSTATUSREGISTER (ISR)DMA00HCP0HF3HF2HCIEHTIEHOST TRANSMIT INTERRUPT ENABLE0HF011AVAILABLE FOR HOST COMMANDP:$007EX:$FFEB23HIGH BYTEMIDDLE BYTE0HRIE00HRDFLOW BYTE4.
DSP56002 WRITES DATA TO HTX, WHICH CLEARS HTDE IN HSR.FAST INTERRUPTORLONG INTERRUPTHOST TRANSMIT DATA VECTORP:$0022P:$00003. IF HTIE = 1, AND INTERRUPTS ARE ENABLED, THEN EXCEPTIONPROCESSING BEGINS.X:$FFE87HF1VIEW FROM HOSTHTDEHOST TRANSMIT DATA EMPTY02. DSP56002 MAY POLL HTDE.X:$FFE971. WHEN HTDE = 1, THEN HTX IS EMPTY.Figure 5-33 Data Transfer from DSP to Host8. IF RREQ = 1, THEN HREQ PIN IS ASSERTED TO INTERRUPT HOST.$0$277. THE TRANSFER SETS RXDF FOR THE HOST TO POLL.LAST READRXHRXM$576. WHEN RXDF = 0 AND HTDE = 0, THEN TRANSFER OCCURS.5. READ OF RXL BY HOST CLEARS RXDF IN ISR.VIEW FROM HOSTFreescale Semiconductor, Inc...HOST RECEIVEDATAREGISTER (HSR)HOST CONTROLREGISTER (HCR)HOST STATUSREGISTER (HSR)Freescale Semiconductor, Inc.HOST INTERFACE (HI)MOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI);****************************************; MAIN PROGRAM...
transmit 24-bit data to hostFreescale Semiconductor, Inc...;****************************************ORGP:$40MOVEPMOVEPMOVEP#1,X:PBC#$0C00,X:IPR#0,X:HCR;Turn on Host Port;Turn on host interrupt;Turn off XMT and RCV interruptsMOVEJCLR#0,SR#3,X:HSR,*;Unmask interrupts;Wait for HF0 (from host) set to 1ANDX0,AJEQLOOPMOVEP#$2,X:HCR;Enable host transmit interruptJMP*;Now wait for interruptFigure 5-34 Main Program - Transmit 24-Bit Data to Host;***********************************;TRANSMIT to Host Interrupt Routine;************************************XMTMOVEPMOVEPRTI#$123456,X:HTX#0,X:HCR;Test value to transmit;Turn off XMT InterruptENDFigure 5-35 Transmit to HI Routine5.3.6.3DMA Data TransferThe DMA mode allows the transfer of 8-, 16- or 24-bit data through the DSP HI under thecontrol of an external DMA controller. The HI provides the pipeline data registers and thesynchronization logic between the two asynchronous processor systems.
The DSP hostexceptions provide cycle-stealing data transfers with the DSP internal or external memory. This technique allows the DSP memory address to be generated using any of theMOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 55Freescale Semiconductor, Inc.HOST INTERFACE (HI)Freescale Semiconductor, Inc...DSP addressing modes and modifiers. Queues and circular sample buffers are easily created for DMA transfer regions. The host exceptions can be programmed as high priorityfast or long exception service routines.
The external DMA controller provides the transfersbetween the DSP HI registers and the external DMA memory. The external DMA controller must provide the address to the external DMA memory; however, the address of theselected HI register is provided by a DMA address counter in the HI.DMA transfers can only be in one direction at a time; however, the host processor canaccess any of the registers not in use during the DMA transfer by deasserting HACK andusing HEN and HA0-HA2 to transfer data.
The host can therefore transfer data in the otherdirection during the DMA operation using polling techniques.+5 VDMACONTROLLERDSP56002HOST INTERFACE1KHREQTRANSFER REQUESTINTERNALADDRESSCOUNTERTRANSFERACKNOWLEDGEHACKH0 - H7MEMORYR/WCONTROLADDRESSDATACharacteristics of Host DMA Mode• The HREQ pin is NOT available for host processor interrupts.• TREQ and RREQ select the direction of DMA transfer.— DMA to DSP56002— DSP56002 to DMA— Simultaneous bidirectional DMA transfers are not permitted.• Host processor software polled transfers are permitted in the opposite direction of the DMA transfer.• 8-, 16-, or 24-bit transfers are supported.• 16-, or 24-bit transfers reduce the DSP interrupt rate by a factor of 2 or 3, respectively.Figure 5-36 HI Hardware–DMA Mode5 - 56PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)XFEREQHREQDMACONTROLLERDSP560021Freescale Semiconductor, Inc...XFERACKHACK24-BIT TRANSFER(INTERNAL COUNTER)H(01)M(10)L(11)H(01)M(10)L(11)16-BIT TRANSFER(INTERNAL COUNTER)M(10)L(11)M(10)L(11)M(10)L(11)8-BIT TRANSFER(INTERNAL COUNTER)L(11)HOSTRECEIVEINTERRUPTL(11)L(11)FAST INTERRUPT ROUTINEP:$0020 MOVE X:$FFE8,AP:$0021 MOVE A, Y:(R7)+L(11)L(11)L(11)READ HRX;AND PUT INTO Y MEMORYFigure 5-37 DMA Transfer and Host Interrupts5.3.6.3.1Host To DSP Internal ProcessingThe following procedure outlines the steps that the HI hardware takes to transfer DMAdata from the host data bus to DSP memory (see Figure 5-36 and Figure 5-37).1.2.3.4.HI asserts the HREQ pin when TXDE=1.DMA controller enables data on H0-H7 and asserts HACK.When HACK is asserted, the HI deasserts HREQ.When the DMA controller deasserts HACK, the data on H0-H7 is latched intothe TXH, TXM, TXL registers.5.
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