Сигнальный МП Motorola DSP56002 (1086189), страница 29
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If the byte register written was not TXL (i.e., not $7) the DMA address counterinternal to the HI increments and HREQ is again asserted. Steps 2-5 are thenrepeated.6. If TXL ($7) was written, TXDE will be set to zero and the address counter inthe HI will be loaded with the contents of HM1 and HM0. When TXDE=0, thecontents of TXH:TXM:TXL are transferred to HRX provided HRDF=0. After thetransfer to HRX, TXDE will be set to one, and HREQ will be asserted to startthe transfer of another word from external memory to the HI.7.
When the transfer to HRX occurs within the HI, HRDF is set to one. AssumingHRIE=1, a host receive exception will be generated. The exception routinemust read the HRX to clear HRDF.Note: The transfer of data from the TXH, TXM, TXL registers to the HRX register auto-MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 57Freescale Semiconductor, Inc.HOST INTERFACE (HI)MODES7Freescale Semiconductor, Inc...$00INITHM1HM0HF1HF00TREQ RREQ00Interrupt Mode (DMA Off)0124 Bit DMA Mode1016 Bit DMA Mode118 Bit DMA ModeRESET CONDITIONDMA MODEINTERRUPT MODE (DMA OFF)TREQRREQ000INTERRUPT CONTROL REGISTER (ICR)(READ/WRITE)HREQ PINTREQRREQHREQ PINNo Interrupts (Polling)00No DMA1RXDF Request (Interrupt)01DSP to Host Request (RX)10XDE Request (Interrupt)10Host to DSP Request (TX)11XDF and TXDE Request (Interrupts)11Undefined (Illegal)7$2HREQ0DMA0HF3HF2TRDY TXDE RXDF7X:$FFE9DMA000HF1HF0HCPHTDE HRDFINTERRUPT STATUSREGISTER (ISR)(READ ONLY)HOST STATUSREGISTER (HSR)(READ ONLY)Figure 5-38 Host Bits with TREQ and RREQmatically loads the DMA address counter from the HM1 and HM0 bits in the DMAhost to DSP mode.
This DMA address is used with the HI to place the receivedbyte in the correct register (TXH, TXM, or TXL).Figure 5-37 shows the differences between 24-, 16-, and 8-bit DMA data transfers. Theinterrupt rate is three times faster for 8-bit data transfers than for 24-bit transfers. TXL isalways loaded last.5.3.6.3.2Host to DSP DMA ProcedureThe following procedure outlines the typical steps that the host processor must take tosetup and terminate a host-to-DSP DMA transfer (see Figure 5-39).5 - 58PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLAFor More Information On This Product,Go to: www.freescale.comPORT B9.
TERMINATE DSP DMA MODE BYCLEARING HM1, HM0, AND TREQ.8. TERMINATE DMA CHANNEL.5. HOST IS FREE TO PERFORMOTHER TASKS (i.e., DSP TO HOSTTRANSFER ON A POLLED BASIS).3. TELL DSP56002— WHERE TO STORE DATA (i.e., PROGRAMADDRESS REGISTER R7).— ENABLE INTERRUPT HRIE (CAN BEDONE WITH A HOST COMMAND).2.
INITIALIZE DSP56002 HOST INTERFACE.— MODE 24 BIT DMA— HOST TO DSP— USE INIT BIT TO:SET TXDECLEAR HRDFLOAD DMA COUNTER1. PROGRAM DMA CONTROLLER.— START ADDRESS— BYTE COUNT— TRANSFER DIRECTION— START DMA CHANNELHOST PROCESSORTXMTXL11TXMTXL101100HM01HF3HF1HF2HF0FAST INTERRUPTORLONG INTERRUPTAVAILABLE FOR HOST COMMANDHOST RECEIVE DATA VECTOREXCEPTION VECTOR TABLE7. DMA CONTROLLER INTERRUPTS HOSTWHEN TRANSFERS ARE DONE.P:$007EP:$0020P:$0000HREQPIN0HCIEDSP560024. ASSERT HREQ TO START DMA TRANSFER.0HM1INIT7017Figure 5-39 Host-to-DSP DMA ProcedureTXH01•••TXH1110TXL1001TXHTXM01$0X:$FFE86. DMA CONTROLLER PERFORMS WRITES.WRITE ICRDMA CONTROLLERFreescale Semiconductor, Inc...0HTIEHRIE10TREQ RREQ10HOST CONTROLREGISTER (HCR)INTERRUPTCONTROLREGISTER (ICR)Freescale Semiconductor, Inc.HOST INTERFACE (HI)5 - 59Freescale Semiconductor, Inc.Freescale Semiconductor, Inc...HOST INTERFACE (HI)1. Set up the external DMA controller (1) source address, byte count, direction,and other control registers.
Enable the DMA controller channel.2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1),to select the direction (TREQ=1, RREQ=0), and to initialize the channel settingINIT=1 (see Figure 5-38).3. Initialize the DSP’s destination pointer (3) used in the DMA exception handler(an address register, for example) and set HRIE to enable the HRDF interruptto the DSP CPU. This procedure can be done with a separate host commandexception routine in the DSP. HREQ will be asserted (4) immediately by the HIto begin the DMA transfer.4.
Perform other tasks (5) while the DMA controller transfers data (6) until interrupted by the DMA controller DMA transfer complete interrupt (7). The DSPinterrupt control register (ICR), the interrupt status register (ISR), and RXH,RXM, and RXL registers may be accessed at any time by the host processorbut the TXH, TXM and TXL registers may not be accessed until the DMAmode is disabled.5.
Terminate the DMA controller channel (8) to disable DMA transfers.6. Terminate the DSP HI DMA mode (9) in the ICR by clearing the HM1 and HM0bits and clearing TREQ.The HREQ will be active immediately after initialization is completed (depending on hardware) because the data direction is host to DSP and TXH, TXM, and TXL registers areempty.
When the host writes data to TXH, TXM, and TXL, this data will be immediatelytransferred to HRX. If the DSP is due to work in interrupt mode, HRIE must be enabled.5.3.6.3.3DSP to Host Internal ProcessingThe following procedure outlines the steps that the HI hardware takes to transfer DMAdata from DSP memory to the host data bus.1. On the DSP side of the HI, a host transmit exception will be generated whenHTDE=1 and HTIE=1.
The exception routine must write HTX, thereby settingHTDE=0.2. If RXDF=0 and HTDE=0, the contents of HTX will be automatically transferredto RXH:RXM:RXL, thereby setting RXDF=1 and HTDE=1. Since HTDE=1again on the initial transfer, a second host transmit exception will be generatedimmediately, and HTX will be written, which will clear HTDE again.3.
When RXDF is set to one, the HI’s internal DMA address counter is loaded(from HM1 and HM0) and HREQ is asserted.4. The DMA controller enables the data from the appropriate byte register ontoH0-H7 by asserting HACK. When HACK is asserted, HREQ is deasserted by5 - 60PORT BFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.HOST INTERFACE (HI)the HI.5. The DMA controller latches the data presented on H0-H7 and deassertsHACK. If the byte register read was not RXL (i.e., not $7), the HI’s internalDMA counter increments, and HREQ is again asserted.
Steps 3, 4, and 5 arerepeated until RXL is read.6. If RXL was read, RXDF will be set to zero and, since HTDE=0, the contents ofHTX will be automatically transferred to RXH:RXM:RXL, and RXFD will be setto one. Steps 3, 4, and 5 are repeated until RXL is read again.Freescale Semiconductor, Inc...Note:The transfer of data from the HTX register to the RXH:RXM:RXL registers automatically loads the DMA address counter from the HM1 and HM0 bits when in theDMA DSP–HOST mode.
This DMA address is used within the HI to place the appropriate byte on H0-H7.5.3.6.3.4DSP to Host DMA ProcedureThe following procedure outlines the typical steps that the host processor must take tosetup and terminate a DSP-to-host DMA transfer (see Figure 5-40).1. Set up the DMA controller (1) destination address, byte count, direction, andother control registers. Enable the DMA controller channel.2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1),the direction (TREQ=0, RREQ=1), and setting INIT=1 (see Figure 5-40 foradditional information on these bits).3.
Initialize the DSP’s source pointer (3) used in the DMA exception handler (anaddress register, for example), and set HTIE to enable the DSP host transmitinterrupt. This could be done by the host processor with a host commandexception routine.The DSP host transmit exception will be activated immediately after HTIE isset. The DSP CPU will move data to HTX. The HI circuitry will transfer the contents of HTX to RXH:RXM:RXL, setting RXDF which asserts HREQ. AssertingHREQ (4) starts the DMA transfer from RXH, RXM, and RXL to the host processor.4. Perform other tasks (5) while the DMA controller transfers data (6) until interrupted by the DMA controller DMA complete interrupt (7). The DSP interruptcontrol register (ICR), the interrupt status register (ISR), and TXH, TXM, andTXL may be accessed at any time by the host processor but the RXH, RXMand RXL registers may not be accessed until the DMA mode is disabled.5. Terminate the DMA controller channel (8) to disable DMA transfers.6.
Terminate the DSP HI DMA mode (9) in the Interrupt Control Register (ICR) byclearing the HM1 and HM0 bits and clearing RREQ.MOTOROLAPORT BFor More Information On This Product,Go to: www.freescale.com5 - 615 - 62For More Information On This Product,Go to: www.freescale.comPORT B9. TERMINATE DSP DMA MODE BYCLEARING HM1, HM0, AND TREQ.8. TERMINATE DMA CHANNEL.5. HOST IS FREE TO PERFORMOTHER TASKS (i.e., DSP TO HOSTTRANSFER ON A POLLED BASIS).3.
TELL DSP56002.— SOURCE POINTER ADDRESS— ENABLE HTIE (CAN BE DONEWITH A HOST COMMAND).2. INITIALIZE DSP56002 HOST INTERFACE.— MODE 24 BIT DMA— HOST TO DSP— USE INIT BIT TO:CLEAR TXDESET HRDFLOAD DMA COUNTER1. PROGRAM DMA CONTROLLER.— START ADDRESS— BYTE COUNT— TRANSFER DIRECTION— START DMA CHANNELHOST PROCESSORRXLRXHRXMRXL1011011011RXMRXL101100HM01HF3HF1HF2HF0FAST INTERRUPTORLONG INTERRUPTAVAILABLE FOR HOST COMMANDHOST TRANSMIT DATA VECTOREXCEPTION VECTOR TABLE7. DMA CONTROLLER INTERRUPTS HOSTWHEN TRANSFERS ARE DONE.P:$007EP:$0022P:$0000HREQ0HCIEDSP560024.
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