Сигнальный МП Motorola DSP56002 (1086189), страница 32
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The communication can be TTL-level signals or,with additional logic, RS232C, RS422, etc.Freescale Semiconductor, Inc...This interface uses three dedicated pins: transmit data (TXD), receive data (RXD), andSCI serial clock (SCLK). It supports industry-standard asynchronous bit rates and protocols as well as high-speed (up to 5 Mbps for a 40-MHz clock) synchronous data transmission.
The asynchronous protocols include a multidrop mode for master/slave operationwith wakeup on idle line and wakeup on address bit capability.The SCI consists of separate transmit and receive sections whose operations can beasynchronous with respect to each other. A programmable baud-rate generator providesthe transmit and receive clocks. An enable vector and an interrupt vector have been included so that the baud-rate generator can function as a general-purpose timer when it isnot being used by the SCI peripheral or when the interrupt timing is the same as that usedby the SCI.
The following is a short list of SCI features:• Three-Pin Interface:TXD – Transmit DataRXD – Receive DataSCLK – Serial Clock• 625 Kbps NRZ Asynchronous Communications Interface (40-MHz System Clock)• 5.0 Mbps Synchronous Serial Mode (40-MHz System Clock)• Multidrop Mode for Multiprocessor Systems:Two Wakeup Modes: Idle Line and Address BitWired-OR Mode• On-Chip or External Baud Rate Generation/Interrupt Timer• Four Interrupt Priority Levels• Fast or Long Interrupts6.3.1SCI I/O PinsThe three SCI pins can be configured as either general-purpose I/O or as a specific SCIpin.
Each pin is independent of the other two, so that if only TXD is needed, RXD andSCLK can be programmed for general-purpose I/O. However, at least one of the threepins must be selected as an SCI pin to release the SCI from reset.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 11Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)SCI interrupts may be enabled by programming the SCI control registers before any of theSCI pins are programmed as SCI functions. In this case, only one transmit interrupt can begenerated because the transmit data register is empty. The timer and timer interrupt willoperate as they do when one or more of the SCI pins is programmed as an SCI function.Freescale Semiconductor, Inc...6.3.1.1Receive Data (RXD)This input receives byte-oriented serial data and transfers the data to the SCI receive shiftregister.
Asynchronous input data is sampled on the positive edge of the receive clock (1× SCLK) if SCKP equals zero. See the DSP56002 Technical Data Sheet for detailed timing information. RXD may be programmed as a general-purpose I/O pin (PC0) when theSCI RXD function is not being used.6.3.1.2Transmit Data (TXD)This output transmits serial data from the SCI transmit shift register. Data changes on thenegative edge of the asynchronous transmit clock (SCLK) if SCKP equals zero.
This output is stable on the positive edge of the transmit clock. See the DSP56002 Technical DataSheet for detailed timing information. TXD may be programmed as a general-purpose I/Opin (PC1) when the SCI TXD function is not being used.6.3.1.3SCI Serial Clock (SCLK)This bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode and from which data is transferredin the synchronous mode. SCLK may be programmed as a general-purpose I/O pin (PC2)when the SCI SCLK function is not being used.
This pin may be programmed as PC2when data is being transmitted on TXD since, in the asynchronous mode, the clock neednot be transmitted. There is no connection between programming the PC2 pin as SCLKand data coming out the TXD pin because SCLK is independent of SCI data I/O.6.3.2SCI Programming ModelThe resources available in the SCI are described before discussing specific examples ofhow the SCI is used. The registers comprising the SCI are shown in Figure 6-8 and Figure6-9. These registers are the SCI control register (SCR), SCI status register (SSR), SCIclock control register (SCCR), SCI receive data registers (SRX), SCI transmit data registers (STX), and the SCI transmit data address register (STXA).
The SCI programmingmodel can be viewed as three types of registers: 1) control – SCR and SCCR in Figure6-8; 2) status – SSR in Figure 6-8; and 3) data transfer – SRX, STX, and STXA in Figure6-9. The following paragraphs describe each bit in the programming model.6 - 12PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLA01614STIR(0)15SCKP(0)For More Information On This Product,Go to: www.freescale.comPORT C01614RCM(0)15TCM(0)SCP(0)13COD(0)12TIE(0)TMIE(0)01213CD11(0)11RIE(0)11CD10(0)10ILIE(0)10CD9(0)9TE(0)9CD8(0)8RE(0)88CD6(0)CD5(0)5PE(0)5WAKE(0)54CD4(0)4OR(0)4SBK(0)CLOCK DIVIDER BITSCD7(0)6FE(0)R8(0)76RWU(0)67WOMS(0)72CD3(0)3IDLE(0)3CD2(0)2RDRF(0)2SSFTD WDS2(0)(0)30CD1(0)1TRNE(1)0SCI STATUS REGISTER (SSR)(READ ONLY)WORD SELECT BITSSCI SHIFT DIRECTIONSEND BREAKWAKEUP MODE SELECTRECEIVER WAKEUP ENABLEWIRED - OR MODE SELECTRECEIVER ENABLESCI CONTROL REGISTER (SCR)(READ/WRITE)CD0(0)0SCI CLOCK CONTROLREGISTER (SCCR)(READ/WRITE)TRANSMITTER EMPTYTRANSMITTER DATA REGISTER EMPTYRECEIVE DATA REGISTER FULLIDLE LINE FLAGTDRE(1)1WDS1 WDS0(0)(0)1Figure 6-8 SCI Programming Model – Control and Status RegistersNOTE: The number in parentheses is the condition of the bit after hardware reset.TRANSMIT CLOCK SOURCE BITRECEIVE CLOCK SOURCE BITCLOCK PRESCALERCLOCK OUTPUT DIVIDERX:$FFF223RECEIVED BIT 8FRAMING ERROR FLAGPARITY ERROR FLAGOVERRUN ERROR FLAGX:$FFF123SCI CLOCK POLARITYTIMER INTERRUPT RATETIMER INTERRUPT ENABLETRANSMIT INTERRUPT ENABLERECEIVE INTERRUPT ENABLEIDLE LINE INTERRUPT ENABLETRANSMITTER ENABLEX:$FFF023Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)6 - 13Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)2316 158 70SRXX:$FFF6SCI RECIEVE DATA REGISTER HIGH (READ ONLY)SRXX:$FFF5SCI RECIEVE DATA REGISTER MID (READ ONLY)SRXX:$FFF4SCI RECEIVE DATA REGISTER LOW (READ ONLY)SCI RECEIVE DATA SHIFT REGISTERRXDFreescale Semiconductor, Inc...NOTE: SRX is the same register decoded at three different addresses.(a) Receive Data Register2316 158 70STXX:$FFF6SCI TRANSMIT DATA REGISTER HIG (WRITE ONLY)STXX:$FFF5SCI TRANSMIT DATA REGISTER MID (WRITE ONLY)STXX:$FFF4SCI TRANSMIT DATA REGISTER LOW (WRITE ONLY)SCI TRANSMITDATA SHIFT REGISTER2316 15TXD8 70X:$FFF3STXASCI TRANSMITDATA ADDRESS REGISTER(WRITE ONLY)NOTES:1.
Bytes are masked on the fly.2. STX is the same register decoded at three different addresses.(b) Transmit Data RegisterFigure 6-9 SCI Programming Model6.3.2.1SCI Control Register (SCR)The SCR is a 16-bit read/write register that controls the serial interface operation. Eachbit is described in the following paragraphs.6.3.2.1.1SCR Word Select (WDS0, WDS1, WDS2) Bits 0, 1, and 2The three word-select bits (WDS0, WDS1, WDS2) select the format of the transmit and receive data.
The formats include three asynchronous, one multidrop asynchronous mode,and an 8-bit synchronous (shift register) mode. The asynchronous modes are compatiblewith most UART-type serial devices and support standard RS232C communication links.6 - 14PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)The multidrop asynchronous modes are compatible with the MC68681 DUART, theM68HC11 SCI interface, and the Intel 8051 serial interface.The synchronous data mode is essentially a high-speed shift register used for I/O expansion and stream-mode channel interfaces. A gated transmit and receive clock that is compatible with the Intel 8051 serial interface mode 0 accomplishes data synchronization. Theword formats are shown in Table 6-1 (also see Figure 6-10 (a) and (b)).Freescale Semiconductor, Inc...Table 6-1 Word FormatsWDS2WDS1WDS0Word Formats0008-Bit Synchronous Data (shift register mode)001Reserved01010-Bit Asynchronous (1 start, 8 data, 1 stop)011Reserved10011-Bit Asynchronous (1 start, 8 data, 1 even parity, 1 stop)10111-Bit Asynchronous (1 start, 8 data, 1 odd parity, 1 stop)11011-Bit Multidrop (1 start, 8 data, 1 data type, 1 stop)111ReservedWhen odd parity is selected, the transmitter will count the number of bits in the data word.If the total is not an odd number, the parity bit is made equal to one and thus produces anodd number.
If the receiver counts an even number of ones, an error in transmission hasoccurred. When even parity is selected, an even number must result from the calculationperformed at both ends of the line or an error in transmission has occurred.The word-select bits are cleared by hardware and software reset.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 15Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MODE 0X:$FFF0210000WDS2WDS1WDS08-BIT SYNCHRONOUS DATA (SHIFT REGISTER MODE)TX(SSFTD = 0)D0D1D2D3D4D5D6D7D6D7 ORDATATYPEONE BYTE FROM SHIFT REGISTERMODE 2Freescale Semiconductor, Inc...X:$FFF0210010WDS2WDS1WDS0TX(SSFTD = 0)10-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 STOP)STARTBITD0D1D2D3D4D5STOPBITMODE 4X:$FFF021100WDS2WDS1WDS0TX(SSFTD = 0)011-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 EVEN PARITY, 1 STOP)STARTBITD0D1D2D3D4D5D6D7 ORDATATYPEEVENPARITYSTOPBITODDPARITYSTOPBITMODE 52X:$FFF010101WDS2WDS1WDS0TX(SSFTD = 0)11-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 ODD PARITY, 1 STOP)STARTBITD0D1D2D3D4D5D6D7 ORDATATYPEMODE 62X:$FFF010110WDS2WDS1WDS0TX(SSFTD = 0)STARTBIT11-BIT ASYNCHRONOUS MULTIDROP (1 START, 8 DATA, 1 DATA TYPE, 1 STOP)D0D1D2D3D4D5D6D7DATATYPESTOPBITData Type: 1 = Address Byte0 = Data ByteNOTES:1.Modes1, 3, and 7 are reserved.2.D0 =LSB;D7 = MSB3.Data is transmitted and received LSB first if SSFTD = 0 or MSB first if SSFTD = 1.(a) SSFTD = 0Figure 6-10 Serial Formats (Sheet 1 of 2)6 - 16PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MODE 0X:$FFF0210000WDS2WDS1WDS08-BIT SYNCHRONOUS DATA (SHIFT REGISTER MODE)TX(SSFTD = 1)D7D6D5D4D3D2D1D0D1D0ONE BYTE FROM SHIFT REGISTERMODE 2Freescale Semiconductor, Inc...X:$FFF0210010WDS2WDS1WDS0TX(SSFTD = 1)STARTBIT10-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 STOP)D7 ORDATATYPED6D5D4D3D2STOPBITMODE 4X:$FFF021100WDS2WDS1WDS0TX(SSFTD = 1)0STARTBIT11-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 EVEN PARITY, 1 STOP)D7 ORDATATYPED6D5D4D3D2D1D0EVENPARITYSTOPBITODDPARITYSTOPBITMODE 52X:$FFF010101WDS2WDS1WDS0TX(SSFTD = 1)STARTBIT11-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 ODD PARITY, 1 STOP)D7 ORDATATYPED6D5D4D3D2D1D0MODE 62X:$FFF010110WDS2WDS1WDS0TX(SSFTD = 1)STARTBIT11-BIT ASYNCHRONOUS MULTIDROP (1 START, 8 DATA, 1 DATA TYPE, 1 STOP)DATATYPED7D6D5D4D3D2D1D0STOPBITData Type: 1 = Address Byte0 = Data ByteNOTES:1.Modes 1, 3, and 7 are reserved.2.D0 = LSB;D7 = MSB3.Data is transmitted and received LSB first if SSFTD = 0 or MSB first if SSFTD = 1.(b) SSFTD = 1Figure 6-10 Serial Formats (Sheet 2 of 2)MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 17Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...6.3.2.1.2SCR SCI Shift Direction (SSFTD) Bit 3The SCI data shift registers can be programmed to shift data in/out either LSB first ifSSFTD equals zero, or MSB first if SSFTD equals one.
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