Сигнальный МП Motorola DSP56002 (1086189), страница 36
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A preamble (TE was toggled)2. A break (SBK was set or was toggled)3. There is data for transmission (TDRE=0)After the current character transmission, if two or more of these commands are set, thetransmitter will execute them in the following priority:1. Preamble2.
Break3. Data6 - 30PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...6.3.3Register Contents After ResetThere are four methods to reset the SCI. Hardware or software reset clears the port control register bits, which configure all I/O as general-purpose input. The SCI will remain inthe reset state while all SCI pins are programmed as general-purpose I/O (CC2, CC1, andCC0=0); the SCI will become active only when at least one of the SCI I/O pins is programmed as not general-purpose I/O.During program execution, the CC2, CC1, and CC0 bits may be cleared (individual reset), which will cause the SCI to stop serial activity and enter the reset state. All SCIstatus bits will be set to their reset state; however, the contents of the interface controlregister are not affected, allowing the DSP program to reset the SCI separately from theother internal peripherals.The STOP instruction halts operation of the SCI until the DSP is restarted, causing theSSR to be reset.
No other SCI registers are affected by the STOP instruction. Table 6-2illustrates how each type of reset affects each register in the SCI.6.3.4SCI InitializationThe correct way to initialize the SCI is as follows:1. Hardware or software reset2. Program SCI control registers3. Configure SCI pins (at least one) as not general-purpose I/OFigure 6-14 and Figure 6-15 show how to configure the bits in the SCI registers. Figure6-14 is the basic initialization procedure showing which registers must be configured. (1)A hardware or software reset should be used to reset the SCI and prevent it from doinganything unexpected while it is being programmed.
(2) Both the SCI interface control register and the clock control register must be configured for any operation using the SCI. (3)The pins to be used must then be selected to release the SCI from reset and (4) beginoperation. If interrupts are to be used, the pins must be selected, and interrupts must beenabled and unmasked before the SCI will operate. The order does not matter; any oneof these three requirements for interrupts can be used to finally enable the SCI.Figure 6-15 shows the meaning of the individual bits in the SCR and SCCR.
The figuresbelow do not assume that interrupts will be used; they recommend selecting the appropriate pins to enable the SCI. Programs shown in Figures Figure 6-20, Figure 6-21, Figure6-28, Figure 6-34, and Figure 6-36 control the SCI by enabling and disabling interrupts.Either method is acceptable.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 31Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Table 6-2 SCI Registers after ResetFreescale Semiconductor, Inc...RegisterBitSCRSSRSCCRSRXSTXSRSHSTSHBitMnemonicBit NumberSCKPSTIRTMIETIERIEILIETEREWOMSRWUWAKESBKSSFTDWDS (2–0)R8FEPEORIDLERDRFTDRETRNETCMRCMSCPCODCD (11–0)SRX (23–0)STX (23–0)SRS (8–0)STS (8–0)15141312111098765432–0765432101514131211–023–16, 15–8, 7–023–08–08–0Reset TypeHW ResetSW ResetIR ResetST Reset000000000000000000001100000––––000000000000000000001100000––––––––––––––––––00000011–––––––––––––––––––––––00000011–––––––––NOTES:SRSH – SCI receive shift register, STSH – SCI transmit shift registerHW – Hardware reset is caused by asserting the external RESET pin.SW – Software reset is caused by executing the RESET instruction.IR – Individual reset is caused by clearing PCC (bits 0–2) (configured for general-purpose I/O).ST – Stop reset is caused by executing the STOP instruction.1 – The bit is set during the xx reset.0 – The bit is cleared during the xx reset.– – The bit is not changed during the xx reset.Table 6-3 (a) through Table 6-4 (b) provide the settings for common baud rates for6 - 32PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)1.
PERFORM HARDWARE OR SOFTWARE RESET.2. PROGRAM SCI CONTROL REGISTERS:a) SCI INTERFACE CONTROL REGISTER — X:$FFF0b) SCI CLOCK CONTROL REGISTER — X:$FFF23. CONFIGURE AT LEAST ONE PORT C CONTROL BIT AS SCI.23X:$FFE10000000000000000CC CC CC CC CC CC CC CC CC PORT C CONTROL876543210 REGISTER (PCC)Freescale Semiconductor, Inc...SCICCxSCLKTXDRXDFunction0GPIO1Serial Interface4. SCI IS NOW ACTIVE.Figure 6-14 SCI Initialization Procedurethe SCI.
The asynchronous SCI baud rates show a baud rate error for the fixed oscillator frequency (see Table 6-3 (a)). These small-percentage baud rate errorsshould allow most UARTs to synchronize. The synchronous applications usually require exact frequencies, which require that the crystal frequency be chosen carefully(see Table 6-4 (a) and Table 6-4 (b)).An alternative to selecting the system clock to accommodate the SCI requirements is toprovide an external clock to the SCI.
For example, a 2.048 MHz bit rate requires a CPUclock of 32.768 MHz. An application may need a 40 MHz CPU clock and an external clockfor the SCI.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 336 - 34X:$FFF0For More Information On This Product,Go to: www.freescale.comPORT CSCKP15STIR14TMIE13RIE11ILIE10TE9WOMS7RWU65000001010011100101110111WAKEStep 2aMULTIDROP = 1POINT TO POINT = 0WIRED - OR MODERE82SSFTD WDS230WDS1 WDS01SCI INTERFACE CONTROL REGISTER (SCR)(READ/WRITE)= 8-BIT SYNCHRONOUS DATA (SHIFT REGISTER MODE)= RESERVED= 10-BIT ASYNCHRONOUS (1 START, 8 DATA, 1 STOP)= RESERVED= 11-BIT ASYNCHRONOUS (1 START, 8 DATA, EVEN PARITY, 1 STOP)= 11-BIT ASYNCHRONOUS (1 START, 8 DATA, ODD PARITY, 1 STOP)= 11-BIT MULTIDROP (1 START, 8 DATA, EVEN PARITY, 1 STOP)= RESERVEDSBK4ENABLE/DISABLERECEIVE DATAENABLE = 1DISABLE = 0ENABLE/DISABLETRANSMIT DATAENABLE = 1DISABLE = 0ENABLE/DISABLERECEIVE INTERRUPTENABLE = 1DISABLE = 0ENABLE/DISABLETRANSMIT INTERRUPTENABLE = 1DISABLE = 0Figure 6-15 SCI General Initialization Detail – Step 2 (Sheet 1 of 2)TIE12BIT 15 = 0BIT 14 = 0BIT 13 = 0BIT 10 = 0BIT 6 = 0BIT 5 = 0BIT 4 = 0BIT 3 = 0SCKPSTIRTMIEILIERWUWAKESBKSSFTD————————SELECT SCI OPERATION:FOR A BASIC CONFIGURATION, SET:STEP 2a.Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAMOTOROLAX:$FFF2STEP 2b.For More Information On This Product,Go to: www.freescale.comPORT C14RCM15TCMCOD12CD1111CD1010CD99CD88CD775CD5Step 2bCD66CD44CD33CD22CD11CD00Figure 6-15 SCI General Initialization Detail – Step 2 (Sheet 2 of 2)SCP13SETCLOCK OUT DIVIDERIF SCLK PIN IS AN OTUPUT ANDCOD = 1SCLK OUTPUT = 16×COD = 0SCLK OUTPUT = 1×SETSCI CLOCK PRESCALERDIVIDE BY 8 = 1DIVIDE BY 1 = 0SETRECEIVE CLOCK SOURCEEXTERNAL CLOCK = 1INTERNAL CLOCK = 0SETTRANSMIT CLOCK SOURCEEXTERNAL CLOCK = 1INTERNAL CLOCK = 0SELECT CLOCK AND DATA RATE:SET THE CLOCK DIVIDER BITS (CD0 - CD11) ACCORDING TO TABLES 11 - 2 OR 11 - 3.SET THE SCI CLOCK PRESCALER BIT (SCP, BIT 13) ACCORDING TO TABLES 11 - 2 OR 11 - 3.Freescale Semiconductor, Inc...SCI CLOCK CONTROL REGISTER (SCCR)(READ/WRITE)Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)6 - 35Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...Table 6-3 (a) Asynchronous SCI Bit Rates for a 40-MHz CrystalBit Rate(BPS)SCPBitDivider Bits(CD0–CD11)Bit RateError, Percent625.0K0$000056.0K0$00A+1.4638.4K0$00F+1.7219.2K0$020-1.3696000$040+0.1680000$04D+0.1548000$081+0.1524001$020-1.3812001$040+0.086001$08103001$1030BPS= f0 ÷ ∏ (64X (7(SCP) + 1) X (CD + 1)); f0=40 MHzSCP=0 or 1CD=0 to $FFFTable 6-3 (b) Frequencies for Exact Asynchronous SCI Bit RatesBit Rate(BPS)SCP BitDivider Bits(CD0–CD11)CrystalFrequency96000$04039,936,00048000$08139,936,00024000$10339,936,00012000$20739,936,0003000$82239,993,00096001$00739,321,60048001$00F39,321,60024001$01F39,321,60012001$04039,360,0003001$10339,936,000f0=BPS X 64X (7(SCP) + 1)X(CD + 1))SCP=0 or 1CD=0 to $FFF6 - 36PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...Table 6-4 (a) Synchronous SCI Bit Rates for a 32.768-MHz CrystalBaud Rate(BPS)SCP BitDivider Bits(CD0–CD11)Baud RateError,Percent4.096M0$0000128K0$01F064K0$03F056K0$048-0.19532K0$07F016K0$0FF080000$1FF040000$3FF020000$7FF010000$FFF0BPS= f0 ÷ (8 × (7(SCP) + 1) × (CD + 1)); f0=32.768 MHzSCP=0 or 1CD=0 to $FFFTable 6-4 (b) Frequencies for Exact Synchronous SCI Bit RatesBit Rate(BPS)SCP BitDivider Bits(CD0–CD11)CrystalFrequency2.048M0$00132.768 MHz1.544M0$00237.056 MHz1.536M0$00236.864 MHzf0=BPS × 8 × (7(SCP) + 1) × (CD + 1)SCP=0 or 1CD=0 to $FFF6.3.5SCI ExceptionsThe SCI can cause five different exceptions in the DSP (see Figure 6-53).
These exceptions are as follows:1. SCI Receive Data – caused by receive data register full with no receive errorconditions existing. This error-free interrupt may use a fast interrupt serviceMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 37Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)PROGRAM MEMORY SPACEEXCEPTIONSTARTINGADDRESSFreescale Semiconductor, Inc...EXCEPTION SOURCETWO WORDS PER VECTOR$0000HARDWARE RESET$0002STACK ERROR$0004TRACE$0006SWI (SOFTWARE INTERRUPT)$0008IRQA EXTERNAL HARDWARE INTERRUPT$000AIRQB EXTERNAL HARDWARE INTERRUPT$000CSSI RECEIVE DATA$000ESSI RECEIVE DATA WITH EXCEPTION STATUS$0010SSI TRANSMIT DATA$0012SSI TRANSMIT DATA WITH EXCEPTION STATUS$0014SCI RECEIVE DATA$0016SCI RECEIVE DATA WITH EXCEPTION STATUS$0018SCI TRANSMIT DATA$001ASCI IDLE LINE$001CSCI TIMER$001ERESERVED$0020HOST RECEIVE DATA$0022HOST TRANSMIT DATA$0024HOST COMMAND (DEFAULT)$0026AVAILABLE FOR HOST COMMAND$0028AVAILABLE FOR HOST COMMANDEXTERNAL INTERRUPTSINTERNALINTERRUPTSEXTERNALINTERRUPTSSYNCHRONOUSSERIALINTERFACEINTERNALINTERRUPTS•••SERIALCOMMUNICATIONSINTERFACEHOSTINTERFACE$003AAVAILABLE FOR HOST COMMAND$003CTIMER$003EILLEGAL INSTRUCTION$0040AVAILABLE FOR HOST COMMAND$007EAVAILABLE FOR HOST COMMANDINTERNALINTERRUPTS•••Figure 6-16 SCI Exception Vector Locations6 - 38PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)routine for minimum overhead.
This interrupt is enabled by SCR bit 11 (RIE).Freescale Semiconductor, Inc...2. SCI Receive Data with Exception Status – caused by receive data register fullwith a receiver error (parity, framing, or overrun error). The SCI status registermust be read to clear the receiver error flag. A long interrupt service routineshould be used to handle the error condition.
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