Сигнальный МП Motorola DSP56002 (1086189), страница 39
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THIS QUEUES THE PREAMBLE TO FOLLOW THE LAST BYTE.WRITE THE FIRST BYTE TO FOLLOW THE PREAMBLE INTO SRX.MARKS (ONES)2SSFTD WDS2310 OR 11 ONES/ZEROS WILL BE SENT DEPENDING ON THE WORD LENGTH SPECIFIED BY WDS2, WDS1, WDS0.X:$FFF01415Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)before the preamble is complete and resume normal transmission. Sending a break follows the same procedure except that instead of clearing TE, SBK is set in the SCR to sendbreaks and then reset to resume normal data transmission.Freescale Semiconductor, Inc...The example presented in Figure 6-28 uses the SCI in the asynchronous mode to transferdata into buffers.
Interrupts are used, allowing the DSP to perform other tasks while thedata transfer is occurring. This program can be tested by connecting the SCI transmit andreceive pins. Equates are used for convenience and readability.The program sets the reset vector to run the program after reset, puts a MOVEP instruction at the SCI receive interrupt vector location, and puts a MOVEP and BCLR at the SCItransmit interrupt vector location so that, after transmitting a byte, the transmitter is disabled until another byte is ready for transmission. The SCI is initialized by setting the interrupt level, which configures the SCR and SCCR, and then is enabled by writing thePCC.
The main program begins by enabling interrupts, which allows data to be received.Data is transmitted by moving a byte of data to the transmit register and by enabling interrupts. The jump-to-self instruction (SEND JMP SEND) is used to wait while interruptstransfer the data.;*******************************************************************************************;SCI ASYNC WITH INTERRUPTS AND SINGLE BYTE BUFFERS*;*******************************************************************************************;*************************************************;SCI and other EQUATES*;*************************************************STARTEQU$0040;Start of programPCCEQU$FFE1;Port C control registerSCREQU$FFF0;SCI interface control registerSCCREQU$FFF2;SCI clock control registerSRXEQU$FFF4;SCI receive registerSTXEQU$FFF4;SCI transmit registerBCREQU$FFFE;Bus control registerIPREQU$FFFF;Interrupt priority registerRXBUFEQU$100;Receive bufferTXBUFEQU$200;Transmit bufferFigure 6-28 SCI Asynchronous Transmit/Receive Example (Sheet 1 of 3);*************************************************MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 53Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...;RESET VECTOR*;*************************************************ORGP:$0000JMPSTART;*************************************************;SCI RECEIVE INTERRUPT VECTOR*;*************************************************ORGP:$0014;Load the SCI RX interrupt vectorsMOVEPX:SRX,Y:(R0)+ ;Put the received byte in the receive;buffer.
This receive routine is;implemented as a fast interrupt.;*************************************************;SCI TRANSMIT INTERRUPT VECTOR*;*************************************************ORGP:$0018;Load the SCI TX interrupt vectorsMOVEPX:(R3)+,X:STX ;Transmit a byte and;increment the pointer in the;transmit buffer.BCLR#12,X:SCR;Disable transmit interrupts;*******************************************************************************************;INITIALIZE THE SCI PORT AND RX, TX BUFFER POINTERS*;*******************************************************************************************ORGP:START;Start the program at location $40ORI#$03,MR;Mask interrupts temporarilyMOVEP#$C000,X:IPR ;Set interrupt priority to 2MOVEP#$0B02,X:SCR ;Disable TX, enable RX interrupts;Enable transmitter, receiver;Point to point;10-bit asynchronous;(1 start, 8 data, 1 stop)MOVEP#$0022,X:SCCR;Use internal TX, RX clocks;9600 BPSMOVEP#>$03,X:PCC ;Select pins TXD and RXD for SCIMOVERXBUF,R0;Initialize the receive bufferMOVETXBUF,R3;Initialize the transmit bufferFigure 6-28 SCI Asynchronous Transmit/Receive Example (Sheet 2 of 3);*************************************************6 - 54PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...;MAIN PROGRAM*;*************************************************ANDI#$FC,MR;Re-enable interruptsMOVE#>$41,X:(R3) ;Move a byte to the transmit bufferMOVER0,X:(R3)BSET#12,X:SCR;and enable interrupts so it;will be transmittedSENDJMPSEND;Normally something more useful;would be put here.END;End of example.Figure 6-28 SCI Asynchronous Transmit/Receive Example (Sheet 3 of 3)6.3.8MultidropMultidrop is a special case of asynchronous data transfer.
The key difference is that a protocol is used to allow networking transmitters and receivers on a single data-transmissionline. Interprocessor messages in a multidrop network typically begin with a destination address. All receivers check for an address match at the start of each message. Receiverswith no address match can ignore the remainder of the message and use a wakeup modeto enable the receiver at the start of the next message.
Receivers with an address matchcan receive the message and optionally transmit an acknowledgment to the sender. Theparticular message format and protocol used are determined by the user’s software.These message formats include point-to-point, bus, token-ring, and custom configurations. The SCI multidrop network is compatible with other leading microprocessors.Figure 6-29 shows a multidrop system with one master and N slaves. The multidrop modeis selected by setting WDS2 equals one, WDS1 equals one, and WDS0 equals zero.
Onepossible protocol is to have a preamble or idle line between messages, followed by an address and then a message. The idle line causes the slaves to wake up and compare theaddress with their own address. If the addresses match, the slave receives the message.If the addresses do not match, the slave ignores the message and goes back to sleep.
Itis also possible to generate an interrupt when an address is received, eliminating the needfor idle time between consecutive messages and addresses. It is also possible for eachslave to look for more than one address, which allows each slave to respond to individualmessages as well as broadcast messages (e.g., a global reset).MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 55X:$FFF06 - 56STIRSCKPTIE12IDLE LINETMIE13For More Information On This Product,Go to: www.freescale.comPORT CTE9RE8EXITRECEIVE REST OFMESSAGE; DO NOTMASK INTERRUPTS.SBK4NOFigure 6-29 11-Bit Multidrop ModeYESDOESHEADER EQUALMY ADDRESS?DOESHEADER EQUALMY ADDRESS?YESWAKE5SSFTD3WDS212EXIT00WDS1 WDS011IGNORE RESTOF MESSAGE.DISABLE RECEIVERAND ITS INTERRUPTS BYSETTING RWU = 1.RXDOTHERSERIALDEVICEADDRESS NLONG MESSAGE FOR MPU 1RWU6RXDMC68HC11ADDRESS 3WOMS7DEVICES IGNORING MESSAGESRXDDSP56002ADDRESS 2ADDRESS 1HEADERILIE10RECEIVER INTERRUPTNORIE11RECEIVER INTERRUPTDEVICE RECEIVINGMESSAGERXDDSP56002ADDRESS 11415Freescale Semiconductor, Inc...TXDDSP56002IDLE LINESCI CONTROL REGISTER (SCCR)(READ/WRITE)Freescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)MOTOROLAFreescale Semiconductor, Inc.SERIAL COMMUNICATION INTERFACE (SCI)Freescale Semiconductor, Inc...6.3.8.1Transmitting Data and Address CharactersTransmitting data and address when the multidrop mode is selected is shown in Figure6-30.
The output sequence shown is idle line, data/address, and the next character. Inboth cases, an “A” is being transmitted. To send data, TE must be toggled to send the idleline, and then “A” must be sent to STX. Sending the “A” to the STX sets the ninth bit in theframe to zero, which indicates that this frame contains data. If the “A” is sent to STXA instead, the ninth bit in the frame is set to a one, which indicates that this frame contains anaddress.6.3.8.2Wired-OR ModeBuilding a multidrop bus network requires connecting multiple transmitters to a commonwire.
The wired-OR mode allows this to be done without damaging the transmitters whenthe transmitters are not in use. A protocol is still needed to prevent two transmitters fromsimultaneously driving the bus. The SCI multidrop word format provides an address fieldto support this protocol. Figure 6-31 shows a multidrop configuration using wired-OR (setbit 7 of the SCR). The protocol shown consists of an idle line between messages; eachmessage begins with an address character. The message can be any length, dependingon the protocol.
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