Сигнальный МП Motorola DSP56002 (1086189), страница 43
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Additional synchronization signals are used to delineate the wordframes. The normal mode of operation is used to transfer data at a periodic rate, but onlyone word per period. The network mode is similar in that it is also intended for periodictransfers; however, it will support up to 32 words (time slots) per period. This mode canbe used to build time division multiplexed (TDM) networks. In contrast, the on-demandmode is intended for nonperiodic transfers of data.
This mode can be used to transfer dataserially at high speed when the data becomes available. This mode offers a subset of theSPI protocol.6.4.1SSI Data and Control PinsThe SSI has three dedicated I/O pins (see Figure 6-1), which are used for transmit data(STD), receive data (SRD), and serial clock (SCK), where SCK may be used by both thetransmitter and the receiver for synchronous data transfers or by the transmitter only forasynchronous data transfers. Three other pins may also be used, depending on the modeselected; they are serial control pins SC0, SC1, and SC2. They may be programmed asSSI control pins in the Port C control register. Table 6-5 shows the definition of SC0, SC1,SC2, and SCK in the various configurations.
The following paragraphs describe the usesof these pins for each of the SSI operating modes. Figure 6-42 and Figure 6-43 show theinternal clock path connections in block diagram form. The receiver and transmitter clockscan be internal or external depending on the SYN, SCD0, and SCKD bits in CRB.6.4.1.1Serial Transmit Data Pin (STD)STD is used for transmitting data from the serial transmit shift register. STD is an outputwhen data is being transmitted. Data changes on the positive edge of the bit clock. STDgoes to high impedance on the negative edge of the bit clock of the last data bit of theword (i.e., during the second half of the last data bit period) with external gated clock, regardless of the mode. With an internally generated bit clock, the STD pin becomes highimpedance after the last data bit has been transmitted for a full clock period, assuminganother data word does not follow immediately.
If a data word follows immediately, therewill not be a high-impedance interval.Codecs label the MSB as bit 0; whereas, the DSP labels the LSB as bit 0. Therefore, whenusing a standard codec, the DSP MSB (or codec bit 0) is shifted out first when SHFD=0, andthe DSP LSB (or codec bit 7) is shifted out first when SHFD=1. STD may be programmedas a general-purpose pin called PC8 when the SSI STD function is not being used.6 - 78PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Table 6-5 Definition of SC0, SC1, SC2, and SCKFreescale Semiconductor, Inc...Asynchronous (SYN=0)SSI Pin Name(Control Bit Name) Continuous Clock Gated Clock(GCK=0)(GCK=1)Synchronous (SYN=1)Continuous Clock(GCK=0)Gated Clock(GCK=1)SC0=0 (in)RXC ExternalRXC ExternalInput F0Input F0SC0=1 (out)(SCD0)RXC InternalRXC InternalOutput F0Output F0SC1=0 (in)FSR ExternalNot UsedInput F1Input F1SC1=1 (out)(SCD1)FSR InternalFSR InternalOutput F1Output F1SC2=0 (in)FST ExternalNot UsedFS* ExternalNot UsedSC2=1 (out)(SCD2)FST InternalFST InternalFS* InternalFS* InternalSCK=0 (in)TXC ExternalTXC External*XC External*XC ExternalSCK=1 (out(SCKD)TXC InternalTXC Internal)*XC Internal*XC InternalTXC – Transmitter ClockRXC – Receiver Clock*XC – Transmitter/Receiver Clock(synchronous operation)FST – Transmitter Frame SyncFSR – Receiver Frame SyncFS* – Transmitter/Receiver Frame Sync(synchronous operation)F0 – Flag 0F1 – Flag 1Table 6-6 SSI Clock Sources, Inputs, and OutputsSYNSCKDSCD0R ClockSourceRX ClockOutT Clock SourceTX Clock OutAsynchronous000EXT, SC0–EXT, SCK–001INTSC0EXT, SCK–010EXT, SC0–INTSCK011INTSC0INTSCKSynchronous100EXT, SCK–EXT, SCK–101EXT, SCK–EXT, SCK–110INTSCKINTSCK111INTSCKINTSCKEXT – External Pin NameINT – Internal Bit ClockMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 79Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)FLAG0 OUT(SYNC MODE)FLAG0 IN(SYNC MODE)WL1, WL0RX WORDCLOCKRX WORDLENGTH DIVIDERSCD0 = 0SYN = 1SYN = 0SC0RX SHIFT REGISTERRCLOCKSYN = 0SCD0 = 1Freescale Semiconductor, Inc...SCD0SYN = 1INTERNAL BIT CLOCKSCKWL1, WL0TCLOCKTX WORDLENGTH DIVIDERTX WORDCLOCKSCKDTX SHIFT REGISTERDIVIDEBY 2FOSCPRESCALEDIVIDE BY 1ORDIVIDE BY 8DIVIDERDIVIDE BY 1TO DIVIDEBY 256PSRPM0 - PM7DIVIDEBY 2Figure 6-42 SSI Clock Generator Functional Block Diagram6.4.1.2Serial Receive Data Pin (SRD)SRD receives serial data and transfers the data to the SSI receive shift register.
SRD maybe programmed as a general-purpose I/O pin called PC7 when the SSI SRD function isnot being used. Data is sampled on the negative edge of the bit clock.6.4.1.3Serial Clock (SCK)SCK is a bidirectional pin providing the serial bit rate clock for the SSI interface. The SCKis a clock input or output used by both the transmitter and receiver in synchronous modesor by the transmitter in asynchronous modes (see Table 6-6).Note: Although an external serial clock can be independent of and asynchronous to theDSP system clock, it must exceed the minimum clock cycle time of 8T (i.e., the system clock frequency must be at least four times the external SSI clock frequency).The SSI needs at least four DSP phases (DSP phase=T) inside each half of theserial clock.6 - 80PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)RX WORDCLOCKDC0 - DC4FSL0, FSL1RECEIVERFRAME RATEDIVIDERSYNCTYPEINTERNAL RX FRAME CLOCKSCD1SCD1 = 1SYN = 0SYN = 0RECEIVECONTROLLOGICSC1RECEIVEFRAME SYNCSCD1 = 0SYN = 1Freescale Semiconductor, Inc...SYN = 1DC0 - DC4FSL0, FSL1FLAG1 IN(SYNC MODE)FLAG1OUT(SYNC MODE)SCD2TX WORDCLOCKTRANSMITTERFRAME RATEDIVIDERTRANSMITCONTROLLOGICSYNCTYPEINTERNAL TX FRAME CLOCKSC2TRANSMITFRAME SYNCFigure 6-43 SSI Frame Sync Generator Functional Block DiagramMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 81Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...6.4.1.4Serial Control Pin (SC0)The function of this pin is determined solely on the selection of either synchronous orasynchronous mode (see Table 6-5 and Table 6-6).
For asynchronous mode, this pin willbe used for the receive clock I/O. For synchronous mode, this pin is used for serial flagI/O. A typical application of flag I/O would be multiple device selection for addressing incodec systems. The direction of this pin is determined by the SCD0 bit in the CRB as described in Table 6-7. When configured as an output, this pin will be either serial output flag0, based on control bit OF0 in CRB, or a receive shift register clock output.
When configured as an input, this pin may be used either as serial input flag 0, which will control statusbit IF0 in the SSISR, or as a receive shift register clock input.Table 6-7 SSI Operation: Flag 0 and Rx ClockSYNGCKSCD0OperationSynchronousContinuousInputFlag 0 InputSynchronousContinuousOutputFlag 0 OutputSynchronousGatedInputFlag 0 InputSynchronousGatedOutputFlag 0 OutputAsynchronousContinuousInputRx Clock – ExternalAsynchronousContinuousOutputRx Clock – InternalAsynchronousGatedInputRx Clock – ExternalAsynchronousGatedOutputRx Clock – Internal6.4.1.5Serial Control Pin (SC1)The function of this pin is determined solely on the selection of either synchronous orasynchronous mode (see Table 6-5 and Table 6-8). In asynchronous mode (such as a single codec with asynchronous transmit and receive), this pin is the receiver frame sync I/O.For synchronous mode with continuous clock, this pin is serial flag SC1 and operates likethe previously described SC0. SC0 and SC1 are independent serial I/O flags but may beused together for multiple serial device selection.
SC0 and SC1 can be used unencodedto select up to two codecs or may be decoded externally to select up to four codecs. Thedirection of this pin is determined by the SCD1 bit in the CRB. When configured as an output, this pin will be either a serial output flag, based on control bit OF1, or it will make thereceive frame sync signal available. When configured as an input, this pin may be usedas a serial input flag, which will control status bit IF1 in the SSI status register, or as a receive frame sync from an external source for continuous clock mode. In the gated clockmode, external frame sync signals are not used.6 - 82PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...Table 6-8 SSI Operation: Flag 1 and Rx Frame SyncSYNGCKSCD1OperationSynchronousContinuousInputFlag 1 InputSynchronousContinuousOutputFlag 1 OutputSynchronousGatedInputFlag 1 InputSynchronousGatedOutputFlag 1 OutputAsynchronousContinuousInputRX Frame Sync – ExternalAsynchronousContinuousOutputRX Frame Sync – InternalAsynchronousGatedInput–AsynchronousGatedOutputRX Frame Sync – Internal6.4.1.6Serial Control Pin (SC2)This pin is used for frame sync I/O (see Table 6-5 and Table 6-9).
SC2 is the frame sync forboth the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. The direction of this pin is determined by the SCD2 bit in CRB. When configured as an output, this pin is the internally generated frame sync signal. When configured asan input, this pin receives an external frame sync signal for the transmitter (and the receiverin synchronous operation). In the gated clock mode, external frame sync signals are not used.Table 6-9 SSI Operation: Tx and Rx Frame SyncSYNGCKSCD2OperationSynchronousContinuousInputTX and RX Frame SyncSynchronousContinuousOutputTX and RX Frame SyncSynchronousGatedInput–SynchronousGatedOutputTX and RX Frame SyncAsynchronousContinuousInputTX Frame Sync – ExternalAsynchronousContinuousOutputTX Frame Sync – InternalAsynchronousGatedInput–AsynchronousGatedOutputTX Frame Sync – Internal6.4.2SSI Programming ModelThe SSI can be viewed as two control registers, one status register, a transmit register, areceive register, and special-purpose time slot register.
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