Сигнальный МП Motorola DSP56002 (1086189), страница 47
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The operational modes are as follows:1. Continuous ClockMode 1 – Normal with Internal Frame SyncMode 2 – Network with Internal Frame SyncMode 3 – Normal with External Frame SyncMode 4 – Network with External Frame Sync2. Gated ClockMode 5 – External Gated ClockMode 6 – Normal with Internal Gated ClockMode 7 – Network with Internal Gated Clock3.
Special Case (Both Gated and Continuous Clock)Mode 8 – On-Demand Mode (Transmitter Only)Mode 9 – Receiver Follows Transmitter Clocking6.4.4Registers After ResetHardware or software reset clears the port control register bits, which configure all I/O asgeneral-purpose input. The SSI will remain in reset while all SSI pins are programmed asgeneral-purpose I/O (CC8–CC3=0) and will become active only when at least one of theSSI I/O pins is programmed as not general-purpose I/O. Table 6-14 shows how each typeof reset affects each SSI register bit.6 - 100PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Table 6-12 Mode and Pin Definition Table – Continuous ClockControl BitsModeFreescale Semiconductor, Inc...MOD GCLK SYN SCD2 SCD1 SCD0 SCKD DC4- TX RXDC0SC0InSC1SC2SCKInOutOutInOutInOutRXC RXC—FSR—FST TXC TXCF1F1—FS*—FSR—FST TXC TXCF1F1—FS*00011XXX110011XXXX1110011XX1221011XXX12200001XXX31RXC RXC00010XXX13RXC RXC FSR——00000XXX33RXC RXC FSR—FST—TXC TXC0010XXXX33F1FS*—*XC10001XXX42RXC RXCFSR FST—TXC TXC10010XX124RXC RXC FSR——10000XXX44RXC RXC FSR—FST—TXC TXC1010XXXX44F1F1FS*—*XC10011XX082—FSR—FST TXC TXC1011XXX089F1F1—FS*10010XX084——FST TXC TXCF0F0RXC RXCF0F0F0F0F0F0RXC RXCF0F0—FSR FSTF1—RXC RXC FSR—*XC*XC*XC*XCTXC TXCFST TXC TXC*XCFST TXC TXC*XC*XC*XCDC4-DC0 = 0 means that bits DC4 = 0, DC3 = 0, DC2 = 0, DC1 = 0, and DC0 = 0DC4-DC0 = 1 means that bits DC4-DC0≠0TXC — Transmitter ClockRXC — Receiver Clock*XC — Transmitter/Receiver Clock (Synchronous Operation)FST — Transmitter Frame SyncFSR — Receiver Frame SyncFS* — Transmitter/Receiver Frame Sync (Synchronous Operation)F0 — Flag 0F1 — Flag 1MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 101Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Table 6-13 Mode and Pin Definition Table – Gated ClockControl BitsModeFreescale Semiconductor, Inc...MOD GCLK SYN SCD2 SCD1 SCD0 SCKD DC4- TX RXDC0SC0SC1SC2SCKInOutInOutInOutInOut010XX11X66—RXC?FSR?FST—TXC011XXX1X66F0F0F0F1?FS*—*XC010XX10X56—RXC?FSR??TXC—010XX00X55RXC—????TXC—011XXX0X55F0F0F1F1??*XC—110XX11087—RXC?FSR?FST—TXC110XX01085RXC—???FST—TXC111XXX1089F0F0F1F1?FS*—*XC010XX01X65RXC—???FST—TXCDC4–DC0=0 means that bits DC4=0, DC3=0, DC2=0, DC1=0, and DC0=0.TXC – Transmitter ClockRXC – Receiver Clock*XC – Transmitter/Receiver Clock (Synchronous Operation)FST – Transmitter Frame SyncFSR – Receiver Frame SyncFS* – Transmitter/Receiver Frame Sync (Synchronous Operation)F0 – Flag 0F1 – Flag 1? – Undefined6 - 102PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Table 6-14 SSI Registers After ResetRegisterNameBit NumberPSRHW ResetSW ResetIndividual ResetST Reset1500––WL(2–0)13,1400––DC(4–0)8–1200––PM(7–0)0–700––RIE1500––TIE1400––RE1300––TE1200––MOD1100––GCK1000––SYN900––FSL1800––FSL0700––SHFD600––SCKD500––SCD(2–0)2–400––OF(1–0)0,100––RDF70000TDE61111ROE50000TUE40000RFS30000TFS20000IF(1–0)0,10000RDRRDR (23–0)23–0––––TDRTDR (23–0)23–0––––RSRRDR (23–0)23–0––––TSRRDR (23–0)23–0––––CRAFreescale Semiconductor, Inc...ResetRegisterDataCRBSSISRNOTES:1.
RSR – SSI receive shift register2. TSR – SSI transmit shift register3. HW – Hardware reset is caused by asserting the external pin RESET.4. SW – Software reset is caused by executing the RESET instruction.5. IR – Individual reset is caused by SSI peripheral pins (i.e., PCC(3–8)) being configured as general-purpose I/O.6. ST – Stop reset is caused by executing the STOP instruction.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 103Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)HARDWARE OR SOFTWARE RESTPROGRAM CRA AND CRBFreescale Semiconductor, Inc...SELECT PINS TO BE USEDPORT C CONTROL REGISTERFigure 6-49 SSI Initialization Block Diagram6.4.5SSI InitializationThe correct way to initialize the SSI is as follows:1.
Hardware, software, SSI individual, or STOP reset2. Program SSI control registers3. Configure SSI pins (at least one) as not general-purpose I/ODuring program execution, CC8–CC3 may be cleared, causing the SSI to stop serial activityand enter the individual reset state. All status bits of the interface will be set to their resetstate; however, the contents of CRA and CRB are not affected.
This procedure allows theDSP program to reset each interface separately from the other internal peripherals.The DSP program must use an SSI reset when changing the MOD, GCK, SYN, SCKD,SCD2, SCD1, or SCD0 bits to ensure proper operation of the interface. Figure 6-49 is aflowchart illustrating the three initialization steps previously listed. Figure 6-50, Figure6-51, and Figure 6-52 provide additional detail to the flowchart.6 - 104PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLAWL1PSRWL013For More Information On This Product,Go to: www.freescale.comPORT CTIERIENOTES:1.
NORMAL — MOD = 02. NETWORK — MOD = 13. FSL1 = 1, FSL0 = 0X:$FFED1415SSI BIT RATE CLOCKDIVIDEBY 2RE13PRESCALERIF PSR = 1, THEN DIVIDE BY 8IF PSR = 0, THEN DIVIDE BY 1X:$FFEC1415MODGCK10DC210DC08SYN9128FSL07PM77(SEE NOTE 3)FSL18Bits/WordDC19SHFD6PM66PM44SCKD5PM11SCD1SCD0OF1••1•••4•SCD2400011OF003000102200001SSI CONTROL REGISTER B (CRB)(READ/WRITE)•••432On-DemandData DrivenfoscSSI CONTROL REGISTER A (CRA)(READ/WRITE)Continuous Periodic(See Note 3)PM0000000DIVIDEBY 2PM22Words/Frame(See Note 2)3PM33Word Transfer Rate(See Note 1)DC4-DC0DIVIDE BY 1TO 256PM55Figure 6-50 SSI CRA Initialization Procedure(SEE NOTES 1 AND 2)TE1110120WL0DC3110WL1DC412Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)6 - 105Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)FRAME SYNC LENGTH 00 = RX AND TX SAMELENGTH1 = RX AND TX DIFFERENTLENGTHFRAME SYNC LENGTH 10 = RX IS WORD LENGTH1 = RX IS BIT LENGTHSHIFT DIRECTION0 = MSB FIRST1 = LSB FIRSTFreescale Semiconductor, Inc...SYNC/ASYNC CONTROL0 = ASYNCHRONOUS1 = SYNCHRONOUSGATED CLOCK CONTROL0 = CONTINUOUS CLOCK1 = GATED CLOCKCLOCK SOURCE DIRECTION0 = INPUT (EXTERNAL)1 = OUTPUT (INTERNAL)SERIAL CONTROLDIRECTION BITS0 = INPUT1 = OUTPUTSSI MODE SELECT0 = NORMAL1 = NETWORK15141312RIETIERETEMOD11GCK10SYN9FSL18FSL0SHFDSCKDSCD2SCD1SCD0765432TRANSMIT ENABLE0 = DISABLE1 = ENABLEOUTPUT FLAG 1IF SYN = 1, SCD1 = 1OF1SC1 PINRECEIVE ENABLE0 = DISABLE1 = ENABLEOUTPUT FLAG 0IF SYN = 1, SCD0 = 1OF0SC0 PIN10OF1OF0TRANSMIT INTERRUPT ENABLE0 = DISABLE1 = ENABLERECEIVE INTERRUPT ENABLE0 = DISABLE1 = ENABLEFigure 6-51 SSI CRB Initialization Procedure6 - 106PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)23X:$FFE10000000000000000CC CC CC CC CC CC CC CC CC8 7 654 3210STDSCKSRDFreescale Semiconductor, Inc...CCxGPIO1Serial InterfaceCSC1SC0Function0PORTSC2PORT C CONTROLREGISTER (PCC)PC0PC1PC2SC0SC1SC2SCKSRDSTDSERIAL CONTROL PIN 0SERIAL CONTROL PIN 1SERIAL CONTROL PIN 2SERIAL CLOCK PINSERIAL RECEIVE DATA PINSERIAL TRANSMIT DATA PINFigure 6-52 SSI Initialization ProcedureFigure 6-52 shows the six control bits in the PCC, which select the six SSI pins as eithergeneral-purpose I/O or as SSI pins.
The STD pin can only transmit data; the SRD pin canonly receive data. The other four pins can be inputs or outputs, depending on how theyare programmed. This programming is accomplished by setting bits in CRA and CRB asshown in Figure 6-46. The CRA (see Figure 6-50) sets the SSI bit rate clock with PSR andPM0–PM7, sets the word length with WL1 and WL0, and sets the number of words in aframe with DC0–DC4. There is a special case where DC4–DC0 equals zero (one wordper frame).
Depending on whether the normal or network mode is selected (MOD=0 orMOD=1, respectively), either the continuous periodic data mode is selected, or the on-demand data driven mode is selected. The continuous periodic mode requires that FSL1equals one and FSL0 equals zero. Figure 6-51 shows the meaning of each individual bitin the CRB. These bits should be set according to the application requirements.Table 6-15 (a) and Table 6-15 (b) provide a convenient listing of PSR and PM0–PM7 settings for the common data communication rates and the highest rate possible for the SSIfor the chosen crystal frequencies. The crystal frequency selected for Table 6-15 (a) is theone used by the DSP56002ADS board; the one selected for Table 6-15 (b) is the closestone to 40 MHz that divides down to exactly 128 kHz. If an exact baud rate is required, thecrystal frequency may have to be selected.
Table 6-16 gives the PSR and PM0–PM7 settings in addition to the required crystal frequency for three common telecommunication frequencies.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 107Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Table 6-15 (b) SSI Bit Ratesfor a 39.936-MHz CrystalFreescale Semiconductor, Inc...Table 6-15 (a) SSI Bit Ratesfor a 40-MHz CrystalBit Rate (BPS)PSRPMBit Rate (BPS)PSRPM10001$4E110001$4DF20001$27020001$26F40001$13840001$13780001$9B80001$9B16K1$4D16K1$4D32K1$2632K1$2664K0$9B64K0$9B128K0$4D128K0$4D10M0$009.984M0$00BPS = fosc ÷ (4 × (7(PSR) +1) × (PM + 1)) wherefosc=39.936 MHzPSR = 0 or 1PM = 0 to $FFFBPS = fosc ÷ (4 × (7(PSR) +1) × (PM + 1)) wherefosc=40 MHzPSR = 0 or 1PM = 0 to $FFFTable 6-16 Crystal Frequencies Required for CodecsBit Rate (BPS)PSRPMCrystalFrequency1.536M0$0536.864 MHz1.544M0$0537.056 MHz2.048M0$0332.678 MHzBPS = fosc ÷ (4 × (7(PSR) +1) × (PM + 1))PSR = 0 or 1PM = 0 to $FFF6 - 108PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)6.4.6SSI ExceptionsThe SSI can generate four different exceptions (see Figure 6-53 and Figure 6-54):1.
SSI Receive Data – occurs when the receive interrupt is enabled, the receivedata register is full, and no receive error conditions exist. Reading RX clearsthe pending interrupt. This error-free interrupt can use a fast interrupt serviceroutine for minimum overhead.Freescale Semiconductor, Inc...2.
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