Сигнальный МП Motorola DSP56002 (1086189), страница 50
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If the frame sync goes high before the frame is completed (or beforethe last bit of the frame is received in the case of a bit frame sync), the current frame syncwill not be recognized, and the receiver will be internally disabled until the next framesync. Frames do not have to be adjacent – i.e., a new frame sync does not have to immediately follow the previous frame.
Gaps of arbitrary periods can occur between frames.The transmitter will be three-stated during these gaps.6.4.7.1.5Shift Direction SelectionSome data formats, such as those used by codecs, specify MSB first other data formats,such as the AES-EBU digital audio, specify LSB first. To interface with devices from bothsystems, the shift registers in the SSI are bidirectional. The MSB/LSB selection is madeby programming SHFD in the CRB.Figure 6-71 illustrates the operation of the SHFD bit in the CRB.
If SHFD equals zero (seeFigure 6-71(a)), data is shifted into the receive shift register MSB first and shifted out ofthe transmit shift register MSB first. If SHFD equals one (see Figure 6-71(b)), data is shifted into the receive shift register LSB first and shifted out of the transmit shift register LSBfirst.6.4.7.2Normal Mode ExamplesThe normal SSI operating mode characteristically has one time slot per serial frame, anddata is transferred every frame sync.
When the SSI is not in the normal mode, it is in thenetwork mode. The MSB is transmitted first (SHFD=0), with overrun and underrun errorsdetected by the SSI hardware. Transmit flags are set when data is transferred from thetransmit data register to the transmit shift register. The receive flags are set when data istransferred from the receive shift register to the receive data register.Figure 6-72 shows an example of using the SSI to connect an MC15500 codec with aDSP56002. No glue logic is needed. The serial clock, which is generated internally by theDSP, provides the transmit and receive clocks (synchronous operation) for the codec.SC2 provides all the necessary handshaking.
Data transfer begins when the frame syncis asserted. Transmit data is clocked out and receive data is clocked in with the serialclock while the frame sync is asserted (word-length frame sync). At the end of the datatransfer, DSP internal interrupts programmed to transfer data to/from will occur, and theSSISR will be updated.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 127:$FFED6 - 128TIERIEFor More Information On This Product,Go to: www.freescale.comPORT CSTDX:$FFEFX:$FFEF1415MOD1110707FSL070 78 70 78 7*0 78 70 7SCD24SCD13TRANSMIT LOW BYTERECEIVE LOW BYTE16 BITRECEIVE LOW BYTERECEIVE LOW BYTESCKD5(a) SHFD = 0TRANSMIT MIDDLE BYTERECEIVE MIDDLE BYTE8 712 BITRECEIVE MIDDLE BYTE8 BIT6SHFDRECEIVE MIDDLE BYTEFSL1800000000OF11OF00SSI CONTROL REGISTER B (CRB)(READ/WRITE)SRDSERIAL TRANSMIT SHIFT REGISTERSERIAL RECEIVE DATA REGISTER (RX)(READ ONLY)24 BITSERIAL RECEIVE SHIFT REGISTER (RX)SERIAL RECEIVE DATA REGISTER (RX)(READ ONLY)SCD02Figure 6-71 CRB SHFD Bit Operation (Sheet 1 of 2)TRANSMIT HIGH BYTE16 152370RECEIVE HIGH BYTE716 150723716 1523RECEIVE HIGH BYTE079SYN16 15GCKRECEIVE HIGH BYTETE12723RE13Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAMOTOROLAX:$FFEFSRDX:$FFEF7For More Information On This Product,Go to: www.freescale.comPORT C7712 BIT0 78 70 78 70 78 70 7(b) SHFD=18 BITTRANSMIT MIDDLE BYTETRANSMIT MIDDLE BYTERECEIVE MIDDLE BYTERECEIVE MIDDLE BYTE8 716 BITTRANSMIT LOW BYTETRANSMIT LOW BYTERECEIVE LOW BYTERECEIVE LOW BYTE0000000024 BITSTDSERIAL TRANSMIT SHIFT REGISTERSERIAL TRANSMIT DATA REGISTER (TX)(WRITE ONLY)SERIAL RECEIVE SHIFT REGISTER (RX)SERIAL RECEIVE DATA REGISTER (RX)(READ ONLY)Figure 6-71 CRB SHFD Bit Operation (Sheet 2 of 2)016 15716 15023TRANSMIT HIGH BYTE716 1500TRANSMIT HIGH BYTERECEIVE HIGH BYTERECEIVE HIGH BYTE16 15723723723Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)6 - 129Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...MC1550xCODEC FILTERANALOGINPUTTX1ANALOGOUTPUTRX0DSP56002TDDRDDTDCRDCTDERCEMSISRDSTDSCKSC2SERIAL CLOCKSERIAL SYNCTRANSMIT DATADSP DATADSP DATARECEIVE DATACODEC DATACODEC DATAFigure 6-72 Normal Mode Example6.4.7.2.1Normal Mode TransmitThe conditions for data transmission from the SSI are as follows:1.
Transmitter is Enabled (TE=1)2. Frame sync (or clock in gated clock mode) is activeWhen these conditions occur in normal mode, the next data word will be transferred fromTX to the transmit shift register, the TDE flag will be set (transmitter empty), and the transmit interrupt will occur if TIE equals one (transmit interrupt enabled.) The new data wordwill be transmitted immediately.The transmit data output (STD) is three-stated, except during the data transmission period. The optional frame sync output, flag outputs, and clock outputs are not three-statedeven if both receiver and transmitter are disabled.The optional output flags are always updated at the beginning of the frame, regardless ofTE. The state of the flag does not change for the entire frame.6 - 130PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Figure 6-73 is an example of transmitting data using the SSI in the normal mode with acontinuous clock, a bit-length frame sync, and 16-bit data words.
The purpose of the program is to interleave and transmit right and left channels in a compact disk player. FourSSI pins are used:1. SC0 is used as an output flag to indicate right-channel data (OF0=1) or left-channel data (OF0=0)2. SC2 is TX and RX frame sync outFreescale Semiconductor, Inc...3. STD is transmit data out4. SCK clocks the transmit data outEquates are set for convenience and readability. Test data is then put in the low X: memory locations.
The transmit interrupt vector contains a JSR instruction (which forms a longinterrupt). The data pointer and channel flag are initialized before initializing CRA andCRB. It is assumed that the DSP CPU and SSI have been previously reset.At this point, the SSI is ready to transmit except that the interrupt is masked because theMR was cleared on reset and Port C is still configured as general-purpose I/O.
Unmaskingthe interrupt and enabling the SSI pins allows transmission to begin. A “jump to self” instruction causes the DSP to hang and wait for interrupts to transmit the data. When aninterrupt occurs, a JSR instruction at the interrupt vector location causes the XMT routineto be executed. Data is then moved to the TX register, and the data pointer is incremented. The flag is tested by the JSET instruction and, if it is set, a jump to left occurs, and thecode for the left channel is executed. If the flag is not set, the code for the right channel isexecuted. In either case, the channel flag in X0 and then the output flag are set to reflectthe channel being transmitted. Control is then returned to the main program, which willwait for the next interrupt.MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 131Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...;*************************************************;SSI and other I/O EQUATES*;*************************************************IPREQU$FFFFCRAEQU$FFECCRBEQU$FFEDPCCEQU$FFE1TXEQU$FFEFFLGEQU$0010ORGX:0DC$AAAA00DC$333300DC$CCCC00DC$F0F000;*************************************************;INTERRUPT VECTOR*;*************************************************ORGP:$0010JSRXMT;*************************************************;MAIN PROGRAM*;*************************************************ORGP:$40MOVE#0,R0MOVE#3,M0MOVE#0,X0MOVEX0,X:FLG;*************************************************;Initialize SSI Port*;*************************************************MOVEP#$3000,X:IPRMOVEP#$401F,X:CRAMOVEP#$5334,X:CRB;Data to transmit.;Pointer to data buffer.;Set modulus to 4.;Initialize channel flag for SSI flag.;Start with right channel first.;Set interrupt priority register for SSI.;Set continuous clock=5.12/32 MHz;word length=16.;Enable TIE and TE; make clock and;frame sync outputs; frame;sync=bit mode; synchronous mode;;make SC0 an output.Figure 6-73 Normal Mode Transmit Example (Sheet 1 of 2)6 - 132PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...;*************************************************;Init SSI Interrupt*;*************************************************ANDI#$FC,MRMOVEP#$01F8,X:PCCJMP*;*************************************************;MAIN INTERRUPT ROUTINE*;*************************************************XMTMOVEPX:(R0);pl,X:TXJSET#0,X:FLG,LEFTRIGHT BCLR#0,X:CRBMOVE#>$01,X0MOVEX0,X:FLGRTILEFTBSET#0,X:CRBMOVE#>$00,X0MOVEX0,X:FLGRTIEND;Unmask interrupts.;Turn on SSI port.;Wait for interrupt.;Move data to TX register.;Check channel flag.;Clear SC0 indicating right channel data;Set channel flag to 1 for next data.;Set SC0 indicating left channel data.;Clear channel flag for next data.Figure 6-73 Normal Mode Transmit Example (Sheet 2 of 2)6.4.7.2.2Normal Mode ReceiveIf the receiver is enabled, a data word will be clocked in each time the frame sync signalis generated (internal) or detected (external).
After receiving the data word, it will be transferred from the SSI receive shift register to the receive data register (RX), RDF will be set(receiver full), and the receive interrupt will occur if it is enabled (RIE=1).The DSP program has to read the data from RX before a new data word is transferredfrom the receive shift register; otherwise, the receiver overrun error will be set (ROE=1).Figure 6-74 illustrates the program that receives the data transmitted by the programshown in Figure 6-73. Using the flag to identify the channel, the receive program receivesthe right- and left-channel data and separates the data into a right data buffer and a leftdata buffer.
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