Сигнальный МП Motorola DSP56002 (1086189), страница 52

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This procedure allows the SSI to synchronize to the network timing.Freescale Semiconductor, Inc...Normal startup sequence for transmission in the first time slot is to write the data to betransmitted to TX, which clears the TDE flag. Then set TE and TIE to enable the transmitter on the next frame sync and to enable transmit interrupts.Alternatively, the DSP programmer may decide not to transmit in the first time slot by writing any data to the time slot register (TSR).

This will clear the TDE flag just as if data weregoing to be transmitted, but the STD pin will remain in the high-impedance state for thefirst time slot. The programmer then sets TE and TIE.When the frame sync is detected (or generated), the first data word will be transferred fromTX to the transmit shift register and will be shifted out (transmitted). TX being empty willcause TDE to be set, which will cause a transmitter interrupt.

Software can poll TDE or useinterrupts to reload the TX register with new data for the next time slot. Software can alsowrite to TSR to prevent transmitting in the next time slot. Failing to reload TX (or writing tothe TSR) before the transmit shift register is finished shifting (empty) will cause a transmitterunderrun. The TUE error bit will be set, causing the previous data to be retransmitted.The operation of clearing TE and setting it again will disable the transmitter after completion of transmission of the current data word until the beginning of the next frame sync period. During that time, the STD pin will be three-stated.

When it is time to disable the transmitter, TE should be cleared after TDE is set to ensure that all pending data is transmitted.The optional output flags are updated every time slot regardless of TE.To summarize, the network mode transmitter generates interrupts every time slot and requires the DSP program to respond to each time slot.

These responses can be:1. Write data register with data to enable transmission in the next time slot2. Write the time slot register to disable transmission in the next time slot3. Do nothing – transmit underrun will occur the at beginning of the next time slot,and the previous data will be transmitted6 - 140PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...Figure 6-78 differs from the program shown in Figure 6-73 only in that it uses the networkmode to transmit only right-channel data.

A time slot is assigned for the left-channel data,which could be inserted by another DSP using the network mode. In the “Initialize SSIPort” section of the program, two words per frame are selected using CRA, and the network mode is selected by setting MOD to one in the CRB. The main interrupt routine,which waits to move the data to TX, only transmits data if the current time slot is for theright channel.

If the current time slot is for the left channel, the TSR is written, whichthree-states the output to allow another DSP to transmit the left channel during the timeslot.;*************************************************;SSI and other I/O EQUATES*;*************************************************IPRCRACRBPCCTXTSRFLGEQUEQUEQUEQUEQUEQUEQUORGDCDCDCDC$FFFF$FFEC$FFED$FFE1$FFEF$FFEE$0010X:0$AAAA00$333300$CCCC00$F0F000;Data to transmit.;*************************************************;INTERRUPT VECTOR*;*************************************************ORGJSRP:$0010XMT;*************************************************;MAIN PROGRAM*;*************************************************ORGP:$40MOVE#0,R0;Pointer to data buffer.MOVE#3,M0;Set modulus to 4.MOVE#0,X0;Initialize user flag for SSI flag.MOVEX0,X:FLG;Start with the right channel.Figure 6-78 Network Mode Transmit Example Program (Sheet 1 of 2)MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 141Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...;*************************************************;Initialize SSI Port*;*************************************************MOVEP #$3000,X:IPR;Set interrupt priority register for SSI.MOVEP #$411F,X:CRA;Set continuous clock=5.12/32 MHz;word length=16.MOVEP #$5B34,X:CRB;Enable TIE and TE; make clock and;frame sync outputs; frame;sync=bit mode; synchronous mode;;make SC0 an output.;*************************************************;Init SSI Interrupt*;*************************************************ANDI#$FC,MR;Unmask interrupts.MOVEP #$01F8,X:PCC;Turn on SSI port.JMP*;Wait for interrupt.;*************************************************;MAIN INTERRUPT ROUTINE*;*************************************************XMTJSET#0,X:FLG,LEFT;Check user flag.RIGHT BCLR#0,X:CRB;Clear SC0 indicating right channel dataMOVEP X:(R0)+,X:TXMove data to TX register.MOVE#>$01,X0;Set user flag to 1MOVEX0,X:FLG;for next data.RTILEFTBSET#0,X:CRB;Set SC0 indicating left channel data.MOVEP X0,X:TSR;Write to TSR register.MOVE#>$00,X0;Clear user flagMOVEX0,X:FLG;for next data.RTIENDFigure 6-78 Network Mode Transmit Example Program (Sheet 2 of 2)6 - 142PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI);*************************************************;SSI and other I/O EQUATES*Freescale Semiconductor, Inc...;*************************************************IPREQU$FFFFSSISR EQU$FFEECRAEQU$FFECCRBEQU$FFEDPCCEQU$FFE1RXEQU$FFEF;*************************************************;INTERRUPT VECTOR*;*************************************************ORGJSRP:$000CRCV;*************************************************;MAIN PROGRAM*;*************************************************ORGMOVEMOVEMOVEMOVEP:$40#0,R0#$08,R1#3,M0#3,M1;Pointer to memory buffer for;received data.

Note data will be;split between two buffers which are;modulus 4.;*************************************************;Initialize SSI Port*;*************************************************MOVEPMOVEPMOVEP#$3000,X:IPR#$4100,X:CRA#$AB00,X:CRB;Set interrupt priority register for SSI.;Set word length = 16 bits.;Enable RIE and RE; synchronous;mode with bit frame sync;;clock and frame sync are;external; SC0 is an input.Figure 6-79 Network Mode Receive Example Program (Sheet 1 of 2)MOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 143Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI);*************************************************;Init SSI Interrupt*;*************************************************ANDIMOVEPJMP#$FC,MR#$01F8,X:PCC*;Unmask interrupts.;Turn on SSI port.;Wait for interrupt.;*************************************************Freescale Semiconductor, Inc...;MAIN INTERRUPT ROUTINE*;*************************************************RCVLEFTRIGHTJSETMOVEPRTIMOVEPRTIEND#0,X:SSISR, RIGHT ;Test SCO flag.X:RX,X:(RO)+;If SCO clear, receive data;into left buffer (R0).X:RX,X:(R1)+;If SCO set, receive data;into right buffer (R1).Figure 6-79 Network Mode Receive Example Program (Sheet 2 of 2)6.4.7.3.2Network Mode ReceiveThe receive enable will occur only after detection of a new data frame with RE set.

Thefirst data word is shifted into the receive shift register and is transferred to the RX, whichsets RDF if a frame sync was received (i.e., this is the start of a new frame). Setting RDFwill cause a receive interrupt to occur if the receiver interrupt is enabled (RIE=1).The second data word (second time slot in the frame) begins shifting in immediately afterthe transfer of the first data word to the RX. The DSP program has to read the data fromRX (which clears RDF) before the second data word is completely received (ready totransfer to RX), or a receive overrun error will occur (ROE=1), and the data in the receivershift register will not be transferred and will be lost.If RE is cleared and set again by the DSP program, the receiver will be disabled after receiving the current time slot in progress until the next frame sync (first time slot).

Thismechanism allows the DSP programmer to ignore data in the last portion of a data frame.Note: The optional frame sync output and clock output signals are not affected, even ifthe transmitter and/or receiver are disabled. TE and RE do not disable bit clock andframe sync generation.6 - 144PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)To summarize, the network mode receiver receives every time slot data word unless thereceiver is disabled. An interrupt can occur after the reception of each data word, or theprogrammer can poll RDF. The DSP program response can be1. Read RX and use the data2.

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