Сигнальный МП Motorola DSP56002 (1086189), страница 49
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Word synchronization is inherent in the serial clock signal.2. Frame Sync generation is optional.SERIAL DATASERIAL CLOCKNOTE: Frame sync is required to tell when data is present.SERIAL DATAFRAME SYNCSERIAL CLOCKX:$FFED1415SCD02OF11Freescale Semiconductor, Inc...OF00SSI CONTROL REGISTER B (CRB)(READ/WRITE)Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAMOTOROLAFor More Information On This Product,Go to: www.freescale.comPORT C77DATA NOT DEFINED0665544332211Figure 6-59 Continuous Clock Timing Diagram (8-Bit Example)NOTES:1. For FSL1 = 0 the frame sync is latched and enables the STD output buffer, but data may not be valid until the rising edge of the bit clock.2.
WL bit frame sync (FSL0 = 0, FSL1 = 0) is not defined for DC = 0 in continuous clock mode.3. Data and flags transition after external frame sync but not before the rising edge of the clock.OUTPUT FLAGSDATA OUT FOR:FSL1 = 0, FSL0 = 0FSL0 = 0, FSL1 = 0FRAME SYNC IN:FSL0 = 0, FSL1 = 1OUTPUT FLAGSFSL0 = 0, FSL1 = 0FRAME SYNC OUT:FSL0 = 0, FSL1 = 1INPUT FLAGS LATCHEDDATA IN LATCHEDDATA OUT (FOR DC = 0, ORNETWORK MODES)DATA OUT (FOR DC > 0)CONTINUOUS CLOCK7Freescale Semiconductor, Inc...(DC = 0)(DC = 0)00Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)6 - 1176 - 118For More Information On This Product,Go to: www.freescale.comPORT C077665544332211Figure 6-60 Internally Generated Clock Timing (8-Bit Example)OUTPUT FLAGS (DC = 0)OUTPUT FLAGS (DC > 0)INPUT FLAGS LATCHEDFRAME SYNC OUT:FSL0 = 0, FSL1 = 0FRAME SYNC OUT:FSL0 = 0, FSL1 = 1DATA IN LATCHEDDATA OUT(DC = 0)GATED CLOCK(DC = 0)DATA OUT(DC > 0)GATED CLOCKOUTPUT (DC>0)Freescale Semiconductor, Inc...(DC = 0)0076Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAMOTOROLAFor More Information On This Product,Go to: www.freescale.comPORT C0776655443322Figure 6-61 Externally Generated Gated Clock Timing (8-BitNOTES:1.
Output enabled on rising edge of first clock input.2. Output disabled on falling edge of last clock pulse.3. tdhgc is guaranteed by circuit design.4. Frame syncs (in or out) are not defined for external gated clock mode.INPUT FLAGS LATCHEDDATA IN LATCHEDDATA OUT(DC = 0)GATED CLOCK(DC = 0)DATA OUT(DC > 0)GATED CLOCKINPUT (DC>0)Freescale Semiconductor, Inc...11007tdhgc ≥ 5 ns6Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Data clock and frame sync signals can be generated internally by the DSP or may be ob-6 - 119Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)START OFFRAMEONE FRAMEWORD TRANSFER FATE (=3)3 WORDS PER FRAMEWORDWORDWORDWORDSERIAL CLOCKFreescale Semiconductor, Inc...FRAME SYNCTRANSMITTER EMPTYINTERNAL INTERRUPTS AND FLAGSTRANSMIT DATAXMIT DATAXMIT DATARECEIVER FULLINTERNAL INTERRUPTS AND FLAGSRECEIVE DATAREC DATAREC DATA3-STATE3-STATEFigure 6-62 Synchronous Communicationtained from external sources. If internally generated, the SSI clock generator is used toderive bit clock and frame sync signals from the DSP internal system clock.
The SSI clockgenerator consists of a selectable fixed prescaler and a programmable prescaler for bitrate clock generation and also a programmable frame-rate divider and a word-length divider for frame-rate sync-signal generation.Figures Figure 6-64 through Figure 6-67 show the definitions of the SSI pins during eachof the four main operating modes of the SSI I/O interface. Figure 6-64 uses a gated clock(from either an external source or the internal clock), which means that frame sync is inherent in the clock. Since both the transmitter and receiver use the same clock (synchronous configuration), both use the SCK pin.
SC0 and SC1 are designated as flags or canbe used as general purpose-parallel I/O. SC2 is not defined if it is an input; SC2 is thetransmit and receive frame sync if it is an output.Figure 6-65 shows a gated clock (from either an external source or the internal clock), whichmeans that frame sync is inherent in the clock. Since this configuration is asynchronous, SCKis the transmitter clock pin (input or output) and SC0 is the receiver clock pin (input or output).SC1 and SC2 are designated as receive or transmit frame sync, respectively, if they are se-6 - 120PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)SSI CONTROL REGISTER B (CRB)(READ/WRITE)X:$FF1514131211109876RIETIERETEMODGCKSYNFSL1FSL0SHFD54SCKD SCD232SCD1 SCD010OF1OF0**ASYNCHRONOUS SYN = 0TRANSMITTERFreescale Semiconductor, Inc...STDFRAMESYNCCLOCKEXTERNAL TRANSMIT CLOCKEXTERNAL TRANSMIT FRAME SYNCSCKSC2INTERNAL CLOCKINTERNAL FRAME SYNCEXTERNAL RECEIVE CLOCKEXTERNAL RECEIVE FRAME SYNCSSI BITCLOCKSC0SC1CLOCKFRAMESYNCSRDRECEIVERNOTE: Transmitter and receiver may have different clocks and frame syncs.* SYNCHRONOUS SYN = 1TRANSMITTERSTDFRAMESYNCCLOCKEXTERNAL CLOCKEXTERNAL FRAME SYNCSCKSSI BITCLOCKSC2INTERNAL CLOCKINTERNAL FRAME SYNCCLOCKFRAMESYNCSRDRECEIVERNOTE: Transmitter and receiver may have the same clock frame syncs.Figure 6-63 CRB SYN Bit OperationMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 121Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)PC8STDPC7SRDPC6SCK (TXC and RXC)SSIPC3PC4PC5SC0FLAG0SC1FLAG1SC2?FSt and FSrFreescale Semiconductor, Inc...Figure 6-64 Gated Clock — Synchronous OperationPC8STDPC7SRDPC6SCK (TXC)SSIPC3PC4PC5SC0SC1SC2RXC?FSr?FStFigure 6-65 Gated Clock — Asynchronous OperationPC8STDPC7SRDPC6SCK (TXC and RXC)SSIPC3PC4PC5SC0SC1SC2FLAG 0FLAG 1FSr and FStFigure 6-66 Continuous Clock — Synchronous OperationPC8STDPC7SRDPC6SCK (TXC)SSIPC3PC4PC5SC0SC1SC2RXCFSrFStFigure 6-67 Continuous Clock — Asynchronous Operation6 - 122PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)lected to be outputs; these bits are undefined if they are selected to be inputs.
SC1 and SC2can also be used as general-purpose parallel I/O.Freescale Semiconductor, Inc...Figure 6-66 shows a continuous clock (from either an external source or the internalclock), which means that frame sync must be a separate signal. SC2 is used for framesync, which can come from an internal or external source. Since both the transmitter andreceiver use the same clock (synchronous configuration), both use the SCK pin. SC0 andSC1 are designated as flags or can be used as general-purpose parallel I/O.Figure 6-67 shows a continuous clock (from either an external source or the internalclock), which means that frame sync must be a separate signal.
SC1 is used for the receive frame sync, and SC2 is used for the transmit frame sync. Either frame sync cancome from an internal or external source. Since the transmitter and receiver use differentclocks (asynchronous configuration), SCK is used for the transmit clock, and SC0 is usedfor the receive clock.6.4.7.1.4Frame Sync SelectionThe transmitter and receiver can operate totally independent of each other. The transmitter can have either a bit-long or word-long frame-sync signal format, and the receiver canhave the same or opposite format. The selection is made by programming FSL0 and FSL1in the CRB as shown in Figure 6-68.1.
If FSL1 equals zero (see Figure 6-69), the RX frame sync is asserted duringthe entire data transfer period. This frame sync length is compatible withMotorola codecs, SPI serial peripherals, serial A/D and D/A converters, shiftregisters, and telecommunication PCM serial I/O.2. If FSL1 equals one (see Figure 6-70), the RX frame sync pulses active for onebit clock immediately before the data transfer period. This frame sync length iscompatible with Intel and National components, codecs, and telecommunication PCM serial I/O.The ability to mix frame sync lengths is useful in configuring systems in which data is received from one type device (e.g., codec) and transmitted to a different type device.FSL0 controls whether RX and TX have the same frame sync length (see Figure 6-68).
IfFSL0 equals zero, RX and TX have the same frame sync length, which is selected byFSL1. If FSL0 equals one, RX and TX have different frame sync lengths, which are selected by FSL1.The SSI receiver looks for a receive frame sync leading edge only when the previousMOTOROLAPORT CFor More Information On This Product,Go to: www.freescale.com6 - 123Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)SSI CONTROL REGISTER B (CRB)(READ/WRITE)X:$FFED1514131211109876RIETIERETEMODGCKSYNFSL1FSL0SHFD**54SCKD SCD232SCD1 SCD010OF1OF0* WORD LENGTH: FSL1 = 0, FSL0 = 0SERIAL CLOCKRX, TX FRAME SYNCRX, TX SERIAL DATAFreescale Semiconductor, Inc...DATADATANOTE: Frame sync occurs while data is valid.* ONE BIT: FSL1 = 1, FSL0 = 0SERIAL CLOCKRX, TX FRAME SYNCRX, TX SERIAL DATADATADATANOTE: Frame sync occurs for one bit time preceding the data.* MIXED FRAME LENGTH: FSL1 = 0, FSL0 = 1SERIAL CLOCKRX FRAME SYNCRX SERIAL DATADATADATADATADATATX FRAME SYNCTX SERIAL DATA* MIXED FRAME LENGTH: FSL1 = 1, FSL0 = 1SERIAL CLOCKRX FRAME SYNCRX SERIAL DATADATADATADATADATATX FRAME SYNCTX SERIAL DATAFigure 6-68 CRB FSL0 and FSL1 Bit Operation6 - 124PORT CFor More Information On This Product,Go to: www.freescale.comMOTOROLAMOTOROLAX:$FFECX:$FFECWL0WL1TIERIERE13TE12For More Information On This Product,Go to: www.freescale.comPORT CDC2010DC10908DC008SHFD6PM6615PM5514PM44INTERNAL INTERRUPTS AND FLAGSSCD02PM22OF11PM11OF00PM00SSI CONTROL REGISTER B (CRB)(READ/WRITE)SSI CONTROL REGISTER A (CRA)(READ/WRITE)CODEC DATADSP DATAFSL1 FRAMESYNC LENGTH0 = WORD CLOCKFSL0FRAME SYNC LENGTH0 = SAME LENGTHSSCKDCLOCK SOURCE DIRECTION1 = OUTPUTSCD2SERIAL CONTROL 2 DIRECTION1 = OUTPUTSCD13PM33INTERNAL INTERRUPTS AND FLAGS07PM77Figure 6-69 Normal Mode Initialization for FLS1=0 and FSL0=0CODEC DATA19RECEIVE DATA010DSP DATA0113 WORD FRAME RATEDC3011TRANSMIT DATAFRAME SYNCSERIAL CLOCKSYNSYNC/ASYNC CONTROL1 = SYNCHRONOUSGCKGATED CLOCK CONTROL0 = CONTINUOUS CLOCKMODSSI MODE SELECT0 = NORMAL1415012DC48-BIT WORD LENGTH00PSR131415Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)6 - 1256 - 126X:$FFEDX:$FFECTIERIERE13For More Information On This Product,Go to: www.freescale.comPORT CTE12SYNSYNC/ASYNC CONTROL1 = SYNCHRONOUSGCKGATED CLOCK CONTROL0 = CONTINUOUSSERIAL DATADC2010DATA 101101019DC109DATA 218DC00807PM77PM55PM44SHFD6DATA 315143PM33SCD02PM22OF11PM11OF00PM00SSI CONTROL REGISTER B (CRB)(READ/WRITE)SSI CONTROL REGISTER A (CRA)(READ/WRITE)DATA 4FSL1 FRAMESYNC LENGTH1 = WL CLOCK FOR RXFSL0FRAME SYNC LENGTH0 = DIFFERENT LENGTHSSCKDCLOCK SOURCE DIRECTION1 = OUTPUTDATA 5SCD2SERIAL CONTROL 2 DIRECTION1 = OUTPUTSCD1CONTINUOUS PERIODICPM66Figure 6-70 Normal Mode Initialization for FSL1=1 and FSL0=0TRANSMIT AND RECEIVEFRAME SYNCSERIAL CLOCKDC30118-BIT WORD LENGTHDC4012MODSSI MODE SELECT0 = NORMAL14WL0WL11500PSR131415Freescale Semiconductor, Inc...Freescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)MOTOROLAFreescale Semiconductor, Inc.SYNCHRONOUS SERIAL INTERFACE (SSI)Freescale Semiconductor, Inc...frame is completed.
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